公开(公告)号：US20150117486A1

公开(公告)日：2015-04-30

申请号：US14066942

申请日：2013-10-30

Applicant: Apple Inc.

Inventor： Yizhang Yang ,  Jun Zhai

IPC: G01K15/00 ,  G01K7/01

CPC classification number: G01K15/005 ,  G01K7/01

Abstract: In some embodiments, a method may be provided for calibrating integrated circuit temperature sensors. The method may include sensing a first temperature using a first temperature sensor and a second temperature using a second temperature sensor. The first temperature sensor may be calibrated and is external to a package of the integrated circuit. The second temperature sensor may be included in the integrated circuit. The method may include increasing a temperature of the integrated circuit. The method may include allowing the integrated circuit and the package to thermally equilibrate over a first period of time. The method may include sensing a first slope of a temperature decay by the first temperature sensor. The method may include sensing a second slope of a temperature decay by the second temperature sensor. The method may include calibrating the second temperature sensor responsive to a difference between the first and second temperatures and the first and second slopes.

Abstract translation: 在一些实施例中，可以提供用于校准集成电路温度传感器的方法。 该方法可以包括使用第一温度传感器感测第一温度，并且使用第二温度传感器来感测第二温度。 第一温度传感器可以被校准，并且在集成电路的封装外部。 第二温度传感器可以包括在集成电路中。 该方法可以包括增加集成电路的温度。 该方法可以包括允许集成电路和封装在第一时间段内热平衡。 该方法可以包括感测第一温度传感器的温度衰减的第一斜率。 该方法可以包括感测第二温度传感器的温度衰减的第二斜率。 该方法可以包括响应于第一和第二温度与第一和第二斜率之间的差异来校准第二温度传感器。

公开(公告)号：US20140361395A1

公开(公告)日：2014-12-11

申请号：US14294903

申请日：2014-06-03

Applicant: Apple Inc.

Inventor： Milind S. Bhagavat ,  Jun Zhai

IPC: H01L27/146 ,  G06K9/00

CPC classification number: G06K9/0002 ,  H01L27/14634 ,  H01L27/14636

Abstract: A sensor includes a sensor array formed on a first side of a substrate and at least one circuit operative to communicate with the sensor array formed on a second side of the substrate. At least one via extends through the substrate to electrically connect the sensor array to the at least one circuit. Placing the at least one circuit on the second side of the substrate allows the sensor array to occupy substantially all of the first side of the substrate.

Abstract translation: 传感器包括形成在基板的第一侧上的传感器阵列和至少一个可操作地与形成在基板的第二侧上的传感器阵列通信的电路。 至少一个通孔延伸穿过衬底以将传感器阵列电连接到至少一个电路。 将至少一个电路放置在基板的第二侧上，使得传感器阵列基本上占据基板的所有第一侧。

公开(公告)号：US20140210107A1

公开(公告)日：2014-07-31

申请号：US13753027

申请日：2013-01-29

Applicant: APPLE INC.

Inventor： Jun Zhai

IPC: H01L23/498 ,  H01L21/50

CPC classification number: H01L23/498 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49861 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L25/03 ,  H01L2224/131 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/136 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83102 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665

Abstract: A top package used in a PoP (package-on-package) package includes two memory die stacked with a redistribution layer (RDL) between the die. The first memory die is encapsulated in an encapsulant and coupled to a top surface of the RDL. A second memory die is coupled to a bottom surface of the RDL. The second memory die is coupled to the RDL with either a capillary underfill material or a non-conductive paste. The RDL includes routing between each of the memory die and one or more terminals coupled to the RDL on a periphery of the die.

Abstract translation: 在PoP（封装封装）封装中使用的顶级封装包括两个在管芯之间堆叠有再分配层（RDL）的存储器管芯。 第一个存储器管芯封装在密封剂中并耦合到RDL的顶部表面。 第二存储器管芯耦合到RDL的底表面。 第二个存储器管芯使用毛细管底部填充材料或非导电浆料与RDL耦合。 RDL包括在每个存储管芯与耦合到管芯周边上的RDL的一个或多个端子之间的布线。

公开(公告)号：US12261132B2

公开(公告)日：2025-03-25

申请号：US18485709

申请日：2023-10-12

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/544 ,  H01L23/58

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：US20250014960A1

公开(公告)日：2025-01-09

申请号：US18348934

申请日：2023-07-07

Applicant: Apple Inc.

Inventor： Jiongxin LU ,  Kunzhong Hu ,  Jun Zhai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

Abstract: Various embodiments of an integrated circuit (IC) die package are disclosed. An IC die package includes an IC die, an interposer structure electrically connected to the IC die, a first bonding structure, a second bonding structure, and a molding compound layer. The first bonding structure includes a first dielectric layer disposed on the IC die and a first conductive plug disposed in the first dielectric layer. The second bonding structure includes a second dielectric layer disposed on the interposer structure and a second conductive plug disposed in the second dielectric layer. The molding compound layer includes a mold region and a mold cavity.

公开(公告)号：US20240421126A1

公开(公告)日：2024-12-19

申请号：US18598938

申请日：2024-03-07

Applicant: Apple Inc.

Inventor： Chi Nung Ni ,  Wei Chen ,  Weiming Chris Chen ,  Vidhya Ramachandran ,  Jie-Hua Zhao ,  Suk-Kyu Ryu ,  Myung Jin Yim ,  Chih-Ming Chung ,  Jun Zhai ,  Young Doo Jeon ,  Seungjae Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/58 ,  H01L29/06

Abstract: Integrated circuit (IC) structures, electronic modules, and methods of fabrication are described in which direct bonded interfaces are removed at corners or edges to counteract the potential for non-bonding or delamination. This can be accomplished during singulation, in which a side recess is formed through an entire thickness of an electronic component and into a direct bonded die, followed by final singulation of the IC structure.

公开(公告)号：US20240395686A1

公开(公告)日：2024-11-28

申请号：US18324612

申请日：2023-05-26

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai ,  Kunzhong Hu ,  Arun Sasi ,  Balaji Nandhivaram Muthuraman ,  Zezhou Liu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

Abstract: Electronic packages and electronic systems are described in which a package redistribution layer of the electronic package includes structural features such a via line connections to reduce stress concentration, particularly when the package redistribution layer is formed of organic dielectric materials.

公开(公告)号：US20240249989A1

公开(公告)日：2024-07-25

申请号：US18158090

申请日：2023-01-23

Applicant: Apple Inc.

Inventor： Wei Chen ,  Balaji Nandhivaram Muthuraman ,  Arun Sasi ,  Jie-Hua Zhao ,  Suk-Kyu Ryu ,  Jun Zhai ,  Dominic Morache ,  Young Doo Jeon

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/34

CPC classification number: H01L23/3157 ,  H01L23/34 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/17055 ,  H01L2924/10162 ,  H01L2924/1811 ,  H01L2924/182

Abstract: Microelectronic structures with selectively applied underfill material and/or edge bond material are described. In an embodiment, isolated underfill regions and/or edge bond regions are applied to adjacent to one or more edges of an electronic device and form a plurality of vent openings along the one or more edges.

公开(公告)号：US11967528B2

公开(公告)日：2024-04-23

申请号：US18307554

申请日：2023-04-26

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L21/66 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L21/77 ,  H01L22/20 ,  H01L24/32 ,  H01L24/73 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18 ,  H01L24/17 ,  H01L2224/12105 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/1703 ,  H01L2224/17181 ,  H01L2224/24195 ,  H01L2924/12 ,  H01L2924/1205 ,  H01L2924/1206 ,  H01L2924/1427 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US20240105702A1

公开(公告)日：2024-03-28

申请号：US18178820

申请日：2023-03-06

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jiongxin Lu ,  Kunzhong Hu ,  Jun Zhai ,  Sanjay Dabral

IPC: H01L25/18 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/36 ,  H01L25/00

CPC classification number: H01L25/18 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/36 ,  H01L24/08 ,  H01L24/13 ,  H01L24/32 ,  H01L24/80 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/13082 ,  H01L2224/32245 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Semiconductor packages formed utilizing wafer reconstitution and optionally including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.