摘要:
A method of forming a package structure with reduced damage to semiconductor dies is provided. The method includes providing a die comprising bond pads on a top surface of the die; forming bumps on the bond pads of the die, wherein the bumps have top surfaces higher than the top surface of the die; mounting the die on a chip carrier, wherein the bumps are attached to the chip carrier; molding the die onto the chip carrier with a molding compound; de-mounting the chip carrier from the die; and forming redistribution traces over, and electrically connected to, the bumps of the die.
摘要:
An enhanced wafer level chip scale packaging (WLCSP) copper electrode post is described having one or more pins that protrude from the top of the electrode post. When the solder ball is soldered onto the post, the pins are encapsulated within the solder material. The pins not only add shear strength to the soldered joint between the solder ball and the electrode post but also create a more reliable electrical connection due to the increased surface area between the electrode post/pin combination and the solder ball. Moreover, creating an irregularly shaped solder joint retards the propagation of cracks that may form in the intermetal compounds (IMC) layer formed at the solder joint.
摘要:
A method for packaging a semiconductor device disclosed. A substrate comprising a plurality of dies, separated by scribe line areas respectively is provided, wherein at least one layer is overlying the substrate. A portion of the layer within the scribe lines area is removed by photolithography and etching to form openings. The substrate is sawed along the scribe line areas, passing the openings. In alternative embodiment, a first substrate comprising a plurality of first dies separated by first scribe line areas respectively is provided, wherein at least one first structural layer is overlying the first substrate. The first structural layer is patterned to form first openings within the first scribe line areas. A second substrate comprising a plurality of second dies separated by second scribe line areas respectively is provided, wherein at least one second structural layer is overlying the substrate. The second structural layer is patterned to form second openings within the second scribe line areas. The first substrate and the second substrate are bonded to form a stack structure. The stack structure is cut along the first and second scribe line areas, passing the first and second openings.
摘要:
A multi-chip semiconductor package and a fabrication method thereof are provided. At least one first chip is mounted on and electrically connected to an upper surface of a substrate via solder bumps. A preformed package structure having a second chip and a first encapsulation body is mounted on the upper surface of the substrate, wherein outer leads of the preformed package structure are exposed from the first encapsulation body and electrically connected to the upper surface of the substrate. The first encapsulation body, outer leads and substrate form a space where the first chip is received, and a gap is present between the first chip and the first encapsulation body. A second encapsulation body is formed on the upper surface of the substrate to encapsulate the first chip, solder bumps and preformed package structure. A plurality of solder balls are implanted on the lower surface of the substrate.
摘要:
A wafer test method is performed for a wafer prior to forming bumps on the wafer, using a conductive interposer having one side with test pads and the other side with test bumps electrically connected to the test pads. The conductive interposer is mounted on the wafer having a plurality of chips, wherein the test bumps are in electrical contact with bond pads on active surfaces of the chips. Test probes are used to contact the test pads to perform tests for the chips. This wafer test method is beneficially performed prior to forming bumps on the wafer, such that the prior-art drawback of damaging bumps on the wafer by contacting test probes with the bumps on the wafer can be eliminated, and the conductive interposer mounted on the wafer prevents the test probes from physical contact with the bond pads on the chips, thereby not damaging the bond pads.
摘要:
A semiconductor package structure for improving electrical performance and a method for fabricating the same are proposed, in which a substrate having at least one pair of passive component pads is provided, wherein a semiconductor chip is attached on the substrate and a passive component is mounted to the passive component pads to locate between the substrate and the semiconductor chip. Thus, the passive component can electrically connect the chip and the substrate simultaneously without arranging an additional conductive trace layer, thereby improving the electrical performance of the semiconductor package structure and reducing the structure size.
摘要:
A wafer test method is performed for a wafer prior to forming bumps on the wafer, using a conductive interposer having one side with test pads and the other side with test bumps electrically connected to the test pads. The conductive interposer is mounted on the wafer having a plurality of chips, wherein the test bumps are in electrical contact with bond pads on active surfaces of the chips. Test probes are used to contact the test pads to perform tests for the chips. This wafer test method is beneficially performed prior to forming bumps on the wafer, such that the prior-art drawback of damaging bumps on the wafer by contacting test probes with the bumps on the wafer can be eliminated, and the conductive interposer mounted on the wafer prevents the test probes from physical contact with the bond pads on the chips, thereby not damaging the bond pads.
摘要:
A substrate structure of Flip Chip package includes a plurality of patterned circuit layers alternately stacking up with at least an insulative layer for isolating the patterned circuit layers. The patterned circuit layers are electrically connected each other wherein one of the patterned circuit layers is positioned on the surface of the substrate. The patterned circuit layer includes a plurality of first mounting pads and a plurality of second mounting pads. The solder mask layer covers the patterned circuit layer on the surface of the substrate, and a portion of the surface of the outer edge of the mounting pads while exposes a portion of the surface of the first mounting pads and the whole surface of the second mounting pads.
摘要:
A ball grid array semiconductor package is provided, wherein at least a predetermined position of a conductive trace on a substrate is formed with a discontinuity, allowing the discontinuity and part of the conductive trace around the discontinuity to be exposed to outside of solder mask applied over the substrate and form a discontinuous pad. The conductive trace having the discontinuous pad is electrically conducted as a solder ball is bonded to the discontinuous pad, and is electrically disconnected when the solder ball is not mounted on the discontinuous pad. As the solder ball is hardly bonded firmly to the discontinuous pad, it can be easily removed from the discontinuous pad to disconnect the conductive trace, and the removed solder ball can be simply mounted back to the discontinuous pad to restore electrical conduction of the conductive trace.
摘要:
A low-profile multi-chip module is provided, wherein two or more chips are integrated in a package unit connected to a printed circuit board (PCB), to provide a manifold level of functionality and data storage capacity. The multi-chip module includes at least a first chip and a second chip connected to a predetermined position on an active surface of the first chip by chip-on-chip technology, allowing the active surface of the first chip to be further mounted to a substrate by flip-chip technology. The substrate is attached to the PCB by surface-mount technology, and interposed between the first chip and the PCB. At least a passive component is mounted on the PCB at a position beside the substrate and underneath the second chip. This structure allows the use of a PCB having a smaller layout area for implementing the multi-chip module, thereby desirably reducing the overall structural profile.