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    NON-CRYSTALLINE INORGANIC LIGHT EMITTING DIODE
    102.
    发明申请
    NON-CRYSTALLINE INORGANIC LIGHT EMITTING DIODE 有权
    非结晶无机发光二极管

    公开(公告)号：US20140175440A1

    公开(公告)日：2014-06-26

    申请号：US13725923

    申请日：2012-12-21

    Applicant: Invensas Corporation

    Inventor： Ilyas Mohammed ,  Liang Wang

    IPC: H01L33/18

    CPC classification number: H01L33/0012 ,  H01L33/0095 ,  H01L33/14 ,  H01L33/16 ,  H01L33/18 ,  H01L33/36 ,  H01L33/486 ,  H01L2933/0016 ,  H01L2933/0033 ,  H05B33/14 ,  H05B33/22

    Abstract: Non-crystalline inorganic light emitting diode. In accordance with a first embodiment of the present invention, an article of manufacture includes a light emitting diode. The light emitting diode includes a non-crystalline inorganic light emission layer and first and second semiconducting non-crystalline inorganic charge transport layers surrounding the light emission layer. The light emission layer may be amorphous. The charge transport layers may be configured to inject one type of charge carrier and block the other type of charge carrier.

    Abstract translation: 非结晶无机发光二极管。 根据本发明的第一实施例，制品包括发光二极管。 发光二极管包括非结晶无机发光层和围绕发光层的第一和第二半导体非结晶无机电荷输送层。 发光层可以是无定形的。 电荷输送层可以被配置为注入一种类型的电荷载体并阻挡另一种类型的电荷载体。

    Direct-bonded LED structure contacts and substrate contacts
    103.
    发明授权
    Direct-bonded LED structure contacts and substrate contacts 有权

    公开(公告)号：US11329034B2

    公开(公告)日：2022-05-10

    申请号：US16840245

    申请日：2020-04-03

    Applicant: Invensas Corporation

    Inventor： Min Tao ,  Liang Wang ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

    IPC: H01L21/18 ,  H01L25/16 ,  H01L33/00 ,  H01L25/10 ,  H01L27/12 ,  H01L27/15 ,  H01L25/18 ,  H01L21/321 ,  H01L21/02 ,  H01L23/00 ,  H01L33/06 ,  H01L33/32 ,  H01L33/44 ,  H01L33/46 ,  H01L33/62

    Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

    Formation of a light-emitting diode display
    104.
    发明授权
    Formation of a light-emitting diode display 有权

    公开(公告)号：US11024220B2

    公开(公告)日：2021-06-01

    申请号：US15994987

    申请日：2018-05-31

    Applicant: Invensas Corporation

    Inventor： Liang Wang ,  Rajesh Katkar ,  Javier A. Delacruz ,  Ilyas Mohammed ,  Belgacem Haba

    IPC: G09G3/32 ,  G09G3/20 ,  H01L33/58 ,  H01L33/38

    Abstract: Apparatus and method relating generally to an LED display is disclosed. In such an apparatus, a driver die has a plurality of driver circuits. A plurality of light-emitting diodes, each having a thickness of 10 microns or less and discrete with respect to one another, are respectively interconnected to the plurality of driver circuits. The plurality of light-emitting diodes includes a first portion for a first color, a second portion for a second color, and a third portion for a third color respectively obtained from a first, a second, and a third optical wafer. The first, the second, and the third color are different from one another.

    DIRECT-BONDED LED ARRAYS AND APPLICATIONS
    105.
    发明申请
    DIRECT-BONDED LED ARRAYS AND APPLICATIONS 审中-公开

    公开(公告)号：US20200235085A1

    公开(公告)日：2020-07-23

    申请号：US16840245

    申请日：2020-04-03

    Applicant: Invensas Corporation

    Inventor： Min Tao ,  Liang Wang ,  Rajesh Katkar ,  Cyprian Emeka Uzoh

    IPC: H01L25/16 ,  H01L23/00 ,  H01L21/02 ,  H01L21/321 ,  H01L25/18 ,  H01L27/15 ,  H01L27/12 ,  H01L25/10 ,  H01L33/00

    Abstract: Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

    SYSTEM AND METHOD FOR PROVIDING 3D WAFER ASSEMBLY WITH KNOWN-GOOD-DIES
    106.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING 3D WAFER ASSEMBLY WITH KNOWN-GOOD-DIES 审中-公开

    公开(公告)号：US20200091110A1

    公开(公告)日：2020-03-19

    申请号：US16687498

    申请日：2019-11-18

    Applicant: Invensas Corporation

    Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao

    IPC: H01L23/00 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/304 ,  H01L21/306 ,  H01L25/00 ,  H01L21/683 ,  H01L21/78 ,  H01L21/56

    Abstract: Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.

    Interconnection substrates for interconnection between circuit modules, and methods of manufacture
    107.
    发明授权
    Interconnection substrates for interconnection between circuit modules, and methods of manufacture 有权

    公开(公告)号：US10586759B2

    公开(公告)日：2020-03-10

    申请号：US16017010

    申请日：2018-06-25

    Applicant: Invensas Corporation

    Inventor： Hong Shen ,  Liang Wang ,  Gabriel Z. Guevara ,  Rajesh Katkar ,  Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi

    IPC: H01L23/498 ,  H01L25/065 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

    Abstract: An interposer (110) has contact pads at the top and/or bottom surfaces for connection to circuit modules (e.g. ICs 112). The interposer includes a substrate made of multiple layers (110.i). Each layer can be a substrate (110S), possibly a ceramic substrate, with circuitry. The substrates extend vertically. Multiple interposers are fabricated in a single structure (310) made of vertical layers (310.i) corresponding to the interposers' layers. The structure is diced along horizontal planes (314) to provide the interposers. An interposer's vertical conductive lines (similar to through-substrate vias) can be formed on the substrates' surfaces before dicing and before all the substrates are attached to each other. Thus, there is no need to make through-substrate holes for the vertical conductive lines. Non-vertical features can also be formed on the substrates' surfaces before the substrates are attached to each other. Other embodiments are also provided.

    System and method for providing 3D wafer assembly with known-good-dies
    110.
    发明授权
    System and method for providing 3D wafer assembly with known-good-dies 有权

    公开(公告)号：US10515926B2

    公开(公告)日：2019-12-24

    申请号：US15834658

    申请日：2017-12-07

    Applicant: Invensas Corporation

    Inventor： Hong Shen ,  Liang Wang ,  Guilian Gao

    IPC: H01L21/00 ,  H01L23/00 ,  H01L21/56 ,  H01L21/78 ,  H01L21/683 ,  H01L25/00 ,  H01L21/768 ,  H01L21/306 ,  H01L21/304 ,  H01L21/3105

    Abstract: Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all good dies stacked in 3D wafer assembly. In an implementation, the spaces left by removed defective dies may be filled at least in part with operational dies or with a fill material. Defective dies may be replaced either before or after wafer-to-wafer assembly to eliminate production of defective stacked devices, or the spaces may be left empty. A bottom device wafer may also have its defective dies removed or replaced, resulting in wafer-to-wafer assembly that provides 3D stacks with no defective dies.

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