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157 条记录 (耗时 0.026 秒)

    Contamination control for embedded ferroelectric device fabrication processes
    104.
    发明授权
    Contamination control for embedded ferroelectric device fabrication processes 失效
    嵌入式铁电元件制造工艺的污染控制

    公开(公告)号：US06709875B2

    公开(公告)日：2004-03-23

    申请号：US09925201

    申请日：2001-08-08

    申请人： Stephen R. Gilbert ,  Trace Q. Hurd ,  Laura W. Mirkarimi ,  Scott Summerfelt ,  Luigi Colombo

    发明人： Stephen R. Gilbert ,  Trace Q. Hurd ,  Laura W. Mirkarimi ,  Scott Summerfelt ,  Luigi Colombo

    IPC分类号： H01G706

    CPC分类号： H01L21/6708 ,  H01L21/31122 ,  H01L21/32136 ,  H01L27/0805 ,  H01L27/11502 ,  H01L28/55

    摘要： A ferroelectric device fabrication process is described in which ferroelectric device contaminant substances (e.g., Pb, Zr, Ti, and Ir) that are incompatible with standard CMOS fabrication processes are tightly controlled. In particular, specific etch chemistries have been developed to remove incompatible substances from the backside and edge surfaces of the substrate after a ferroelectric device has been formed. In addition, a sacrificial layer may be disposed over the bottom and edge surfaces (and, in some embodiments, the frontside edge exclusion zone surface) of the substrate to assist in the removal of difficult-to-etch contaminants (e.g., Ir). In this way, the ferroelectric device fabrication process may be integrated with a standard semiconductor fabrication process, whereby ferroelectric devices may be formed together with semiconductor integrated circuits without substantial risk of cross-contamination through shared equipment (e.g., steppers, metrology tools, and the like).

    摘要翻译： 描述了与标准CMOS制造工艺不兼容的铁电体器件污染物质（例如，Pb，Zr，Ti和Ir）被严格控制的铁电器件制造工艺。 特别地，已经开发了特定的蚀刻化学物质，以在形成铁电体器件之后从衬底的背面和边缘表面去除不相容的物质。 此外，牺牲层可以设置在衬底的底部和边缘表面（以及在一些实施例中，前侧边缘排除区域表面）之上，以帮助去除难以蚀刻的污染物（例如Ir）。 以这种方式，铁电体器件的制造工艺可以与标准的半导体制造工艺集成在一起，由此铁电器件可以与半导体集成电路一起形成，而没有通过共享设备（例如，步进器，计量工具和 喜欢）。

    Hardmask designs for dry etching FeRAM capacitor stacks
    105.
    发明授权
    Hardmask designs for dry etching FeRAM capacitor stacks 有权
    硬掩模设计用于干蚀刻FeRAM电容器堆叠

    公开(公告)号：US06534809B2

    公开(公告)日：2003-03-18

    申请号：US09741479

    申请日：2000-12-19

    申请人： Theodore Moise ,  Stephen R. Gilbert ,  Scott R. Summerfelt ,  Guoqiang Xing ,  Luigi Colombo

    发明人： Theodore Moise ,  Stephen R. Gilbert ,  Scott R. Summerfelt ,  Guoqiang Xing ,  Luigi Colombo

    IPC分类号： H01L2994

    CPC分类号： H01L28/55 ,  H01L21/31122 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139

    摘要： An embodiment of the instant invention is a ferroelectric capacitor formed over a semiconductor substrate, the ferroelectric capacitor comprising: a bottom electrode formed over the semiconductor substrate, the bottom electrode comprised of a bottom electrode material (304 of FIG. 4a); a top electrode formed over the bottom electrode and comprised of a first electrode material (306and 308 of FIG. 4a); a ferroelectric material (306 of FIG. 4a) situated between the top electrode and the bottom electrode; and a hardmask formed on the top electrode and comprising a bottom hardmask layer (402 of FIG. 4a) and a top hardmask layer (408 of FIG. 4a) formed on the bottom hardmask layer, the top hardmask layer able to with stand etchants used to etch the bottom electrode, the top electrode, and the ferroelectric material to leave the bottom hardmask layer substantially unremoved during the etch and the bottom hardmask layer being comprised of a conductive material which substantially acts as a hydrogen diffusion barrier.

    摘要翻译： 本发明的一个实施方案是形成在半导体衬底上的铁电电容器，所述铁电电容器包括：形成在所述半导体衬底上的底部电极，所述底部电极由底部电极材料（图4a的304）组成; 形成在底部电极上并由第一电极材料（图4a的306和308）组成的顶部电极; 位于顶部电极和底部电极之间的铁电材料（图4a的306） 以及形成在顶部电极上并包括底部硬掩模层（图4a的402）和形成在底部硬掩模层上的顶部硬掩模层（图4a的408）的硬掩模，所述顶部硬掩模层能够使用支架蚀刻剂 蚀刻底部电极，顶部电极和铁电材料以使蚀刻期间底部硬掩模层基本上不被去除，并且底部硬掩模层由基本上充当氢扩散阻挡层的导电材料构成。

    Metal patterning with adhesive hardmask layer
    106.
    发明授权
    Metal patterning with adhesive hardmask layer 失效
    金属图案与粘合剂硬掩模层

    公开(公告)号：US06211034B1

    公开(公告)日：2001-04-03

    申请号：US09059546

    申请日：1998-04-13

    申请人： Mark R. Visokay ,  Luigi Colombo ,  Paul McIntyre ,  Scott R. Summerfelt

    发明人： Mark R. Visokay ,  Luigi Colombo ,  Paul McIntyre ,  Scott R. Summerfelt

    IPC分类号： H01L218242

    CPC分类号： H01L28/60 ,  H01L21/32139 ,  H01L27/1085

    摘要： An adherent hardmask structure and method of etching a bottom electrode in memory device capacitor structures that dispenses with the need for any adhesion promoter during the etching of the bottom electrode. By using silicon nitride as a hardmask 220, the processing is simplified and a more robust capacitor structure can be produced. Silicon nitride 220 has been shown to yield significantly enhanced adhesion to platinum 210, as compared to silicon oxide formed by any method. Since silicon nitride 220 is oxidation resistant, it advantageously resists any oxygen plasma that might be used in the etch chemistry. This etching process can be used during processing of high-k capacitor structures in DRAMs in the ≧256 Mbit generations.

    摘要翻译： 一种粘附硬掩模结构和蚀刻存储器件电容器结构中的底部电极的方法，其在底部电极的蚀刻期间省去了对任何粘附促进剂的需要。 通过使用氮化硅作为硬掩模220，简化了处理，并且可以产生更坚固的电容器结构。 与通过任何方法形成的氧化硅相比，已经显示氮化硅220产生显着增强的与铂210的粘合性。 由于氮化硅220是抗氧化的，所以它有利地抵抗可能在蚀刻化学中使用的任何氧等离子体。 这种蚀刻工艺可以在> = 256Mbit的DRAM中的高k电容器结构的处理期间使用。

    Adhesion promoting sacrificial etch stop layer in advanced capacitor structures
    107.
    发明授权
    Adhesion promoting sacrificial etch stop layer in advanced capacitor structures 失效
    先进的电容器结构中的粘附促进牺牲蚀刻停止层

    公开(公告)号：US5972722A

    公开(公告)日：1999-10-26

    申请号：US60152

    申请日：1998-04-14

    申请人： Mark R. Visokay ,  Luigi Colombo ,  Paul McIntyre ,  Scott R. Summerfelt

    发明人： Mark R. Visokay ,  Luigi Colombo ,  Paul McIntyre ,  Scott R. Summerfelt

    IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/8242 ,  H01G7/06

    CPC分类号： H01L27/1085 ,  H01L21/31116 ,  H01L28/55 ,  H01L28/60

    摘要： A high-k dielectric capacitor structure and fabrication method that incorporates an adhesion promoting etch stop layer 200 to promote adhesion of the bottom electrode 220 to the interlevel dielectric layer 210 and to provide a well controlled, repeatable and uniform recess prior to the dielectric 230 deposition. By using a sacrificial layer 200, for example silicon nitride (Si3N4), this layer can act as an etch stop during the recess etch to eliminate parasitic capacitance between adjacent capacitor cells A and B and can promote adhesion of the bottom electrode material 220 to the substrate 210.

    摘要翻译： 高k电介质电容器结构和制造方法，其包含粘附促进蚀刻停止层200以促进底部电极220粘附到层间电介质层210，并且在电介质230沉积之前提供良好控制的，可重复的和均匀的凹部 。 通过使用牺牲层200（例如氮化硅（Si 3 N 4）），该层可以在凹陷蚀刻期间用作蚀刻停止以消除相邻的电容器电池A和B之间的寄生电容，并且可以促进底部电极材料220与 衬底210。

    Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device
    109.
    发明申请
    Method of Setting a Work Function of a Fully Silicided Semiconductor Device, and Related Device 审中-公开
    设置完全硅化半导体器件的功能的方法及相关器件

    公开(公告)号：US20120231590A1

    公开(公告)日：2012-09-13

    申请号：US13474927

    申请日：2012-05-18

    申请人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

    发明人： Luigi Colombo ,  Mark R. Visokay ,  James J. Chambers

    IPC分类号： H01L21/28 ,  H01L21/8238

    CPC分类号： H01L21/823835 ,  H01L21/28079 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/28518 ,  H01L21/76819 ,  H01L21/823842

    摘要： A method of setting a work function of a filly silicided semiconductor device, and related device. At least some of the illustrative embodiments are methods comprising forming a gate stack over a semiconductor substrate (the gate stack comprising a dielectric layer, a suicide layer on the dielectric layer that defines a metal-dielectric layer interface, and a polysilicon layer on the suicide layer), depositing a metal layer over the gate stack, annealing to induce a reaction between the polysilicon layer and the metal layer, and delivering a work function-setting dopant to the metal-dielectric layer interface by way of the reaction.

    摘要翻译： 一种设置硅化半导体器件功能的方法及相关器件。 示例性实施例中的至少一些是包括在半导体衬底上形成栅极堆叠的方法（栅极堆叠包括电介质层，介电层上的硅化物层，其限定金属 - 电介质层界面，以及硅化物层 层），在栅极堆叠上沉积金属层，退火以引起多晶硅层和金属层之间的反应，以及通过反应将功函数赋予掺杂剂输送到金属 - 介电层界面。

    Establishing a uniformly thin dielectric layer on graphene in a semiconductor device without affecting the properties of graphene
    110.
    发明授权
    Establishing a uniformly thin dielectric layer on graphene in a semiconductor device without affecting the properties of graphene 有权
    在半导体器件中在石墨烯上建立均匀的薄介电层，而不影响石墨烯的性质

    公开(公告)号：US08198707B2

    公开(公告)日：2012-06-12

    申请号：US12357526

    申请日：2009-01-22

    申请人： Luigi Colombo ,  Sanjay Banerjee ,  Seyoung Kim ,  Emanuel Tutuc

    发明人： Luigi Colombo ,  Sanjay Banerjee ,  Seyoung Kim ,  Emanuel Tutuc

    IPC分类号： H01L29/00 ,  H01L21/18

    CPC分类号： H01L29/1606 ,  H01L21/28255 ,  H01L29/51 ,  H01L29/513

    摘要： A method and semiconductor device for forming a uniformly thin dielectric layer on graphene. A metal or semiconductor layer is deposited on graphene which is located on the surface of a dielectric layer or on the surface of a substrate. The metal or semiconductor layer may act as a nucleation layer for graphene. The metal or semiconductor layer may be subjected to an oxidation process. A thin dielectric layer may then be formed on the graphene layer after the metal or semiconductor layer is oxidized. As a result of synthesizing a metal-oxide layer on graphene, which acts as a nucleation layer for the gate dielectric and buffer to graphene, a uniformly thin dielectric layer may be established on graphene without affecting the underlying characteristics of graphene.

    摘要翻译： 一种用于在石墨烯上形成均匀薄的电介质层的方法和半导体器件。 金属或半导体层沉积在位于介电层表面或基板表面上的石墨烯上。 金属或半导体层可以用作石墨烯的成核层。 可以对金属或半导体层进行氧化处理。 然后可以在金属或半导体层被氧化之后在石墨烯层上形成薄的电介质层。 作为用作栅极电介质的成核层和用于石墨烯的缓冲液的石墨烯上的金属氧化物层的结果，可以在石墨烯上建立均匀的电介质层，而不影响石墨烯的潜在特性。