公开(公告)号：US11101300B2

公开(公告)日：2021-08-24

申请号：US16628920

申请日：2018-07-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Shuhei Nagatsuka ,  Takanori Matsuzaki

IPC: H01L29/10 ,  H01L27/12

Abstract: A semiconductor device enabling high integration is provided. The semiconductor device includes a plug, two capacitors, and two transistors sharing one oxide semiconductor. Each of the transistors includes a stacked-layer structure of a gate insulator and a gate electrode over the oxide semiconductor and an insulator in contact with a side surface of the gate electrode. An opening between the two gate electrodes exposes the insulators in contact with the side surfaces of the gate electrodes, and the plug is in the opening. The capacitor is directly provided over the oxide semiconductor. The side surface area of the capacitor is larger than the projected area of the capacitor.

公开(公告)号：US11094373B2

公开(公告)日：2021-08-17

申请号：US16832289

申请日：2020-03-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki

IPC: G11C11/41 ,  G11C11/412 ,  H01L29/786 ,  G11C14/00 ,  H01L27/12 ,  G11C11/401 ,  H01L29/792 ,  H01L27/11 ,  G11C11/404 ,  G11C11/419

Abstract: A memory device with reduced power consumption is provided. The memory device includes a plurality of memory cells, a precharge circuit, a latch circuit, a bit line pair, and a local bit line pair. The precharge circuit has a function of supplying precharge voltage to the local bit line pair. The plurality of memory cells are connected to the local bit line pair. The latch circuit is connected to the local bit line pair. The latch circuit in a standby state is preferably supplied with the precharge voltage and one of low power supply voltage and high power supply voltage.

公开(公告)号：US11074962B2

公开(公告)日：2021-07-27

申请号：US16640206

申请日：2018-08-27

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya Onuki ,  Takanori Matsuzaki ,  Kiyoshi Kato ,  Shunpei Yamazaki

IPC: G11C11/40 ,  G11C11/4091 ,  G11C5/02 ,  G11C5/06 ,  H01L27/108

Abstract: A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.

公开(公告)号：US10998447B2

公开(公告)日：2021-05-04

申请号：US15451514

申请日：2017-03-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato ,  Tomoaki Atsumi

IPC: G11C16/10 ,  H01L29/786 ,  G11C11/401 ,  G11C11/404 ,  G11C16/04 ,  H01L27/11517 ,  H01L27/11563 ,  H01L27/12 ,  H01L29/24

Abstract: A semiconductor device is provided in which the power consumption can be reduced by reducing the driving voltage and the on-state current can be increased in a period in which a transistor having an extremely low off-state current is brought into an electrically floating state. The semiconductor device comprises a memory cell, a first circuit, and a second circuit. The memory cell includes a first transistor. The first transistor includes a first semiconductor layer, a first gate electrode, and a first back gate electrode. The first gate electrode is connected to a word line. The first back gate electrode is connected to a back gate line. The first circuit supplies a signal for controlling the conduction state of the first transistor to the word line. The second circuit supplies a voltage for controlling the threshold voltage of the first transistor to the back gate line. The second circuit has a function of bringing the back gate line into an electrically floating state in a period in which a signal for controlling the conduction state of the first transistor is supplied to the word line.

公开(公告)号：US10210915B2

公开(公告)日：2019-02-19

申请号：US15613508

申请日：2017-06-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki

IPC: G11C7/10 ,  G11C11/24 ,  G11C11/402 ,  G11C5/02 ,  G11C11/4091 ,  G11C11/4097

Abstract: A memory device with reduced latency is provided. The memory device includes a burst read mode with a burst length of M0 (M0 is an integer greater than or equal to 2), a global sense amplifier array, M0 local memory cell arrays to , and M0 local sense amplifier arrays to . A memory cell includes a transistor and a capacitor. A local memory cell array (J is an integer from 1 to M0) is stacked over a local sense amplifier array . The local memory cell array comprises M0 blocks to differentiated by row, The local sense amplifier array in an idle state retains the data of the block . The block is specified when the local memory cell array is the first local memory cell array to be accessed in a burst read mode.

公开(公告)号：US10192871B2

公开(公告)日：2019-01-29

申请号：US15698138

申请日：2017-09-07

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Kiyoshi Kato

IPC: H01L27/105 ,  H01L23/34 ,  H01L27/12 ,  H01L29/786 ,  H03K17/687 ,  G11C5/02 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/108 ,  G11C11/40 ,  G11C11/4072 ,  G11C11/4094

Abstract: To provide a semiconductor device in which the on-state current is high and the operation speed is high. The semiconductor device includes a transistor, a first circuit, and a second circuit. The transistor includes a first gate and a second gate. The first gate and the second gate overlap with each other with a semiconductor layer positioned therebetween. The first circuit includes a temperature sensor. The temperature sensor obtains temperature information. The first circuit is configured to apply a voltage to the second gate depending on the temperature information. The first circuit preferably includes a comparator. The second circuit is configured to apply a negative voltage to the second gate and hold the negative voltage.

公开(公告)号：US10037294B2

公开(公告)日：2018-07-31

申请号：US15590406

申请日：2017-05-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Wataru Uesugi

IPC: G11C11/4091 ,  G06F13/40 ,  G11C15/04 ,  G06F13/10 ,  G06F13/42 ,  G06F15/80 ,  G06F12/02 ,  G06F12/0831 ,  G11C14/00

CPC classification number: G06F13/40 ,  G06F12/0246 ,  G06F12/0831 ,  G06F13/10 ,  G06F13/4256 ,  G06F15/80 ,  G11C5/025 ,  G11C7/1039 ,  G11C11/4091 ,  G11C14/0027 ,  G11C14/0036 ,  G11C14/0054 ,  G11C14/0072 ,  G11C14/0081 ,  G11C15/04 ,  Y02D10/14 ,  Y02D10/151

Abstract: A semiconductor device including a memory which can perform a pipeline operation is provided. The semiconductor device includes a processor core, a bus, and a memory section. The memory section includes a first memory. The first memory includes a plurality of local arrays. The local array includes a sense amplifier array and a local cell array stacked thereover. The local cell array is provided a memory cell including one transistor and one capacitor. The transistor is preferably an oxide semiconductor transistor. The first memory is configured to generate a wait signal. The wait signal is generated when a request for writing data to the same local array is received over two successive clock cycles from the processor core. The wait signal is sent to the processor core via the bus. The processor core stands by for a request for the memory section on the basis of the wait signal.

公开(公告)号：US09755643B2

公开(公告)日：2017-09-05

申请号：US14967592

申请日：2015-12-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Takahiko Ishizu ,  Tatsuya Onuki

IPC: H03L5/00 ,  H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  G11C5/147 ,  G11C7/04 ,  G11C7/14 ,  G11C8/08 ,  G11C11/403 ,  G11C11/4085 ,  G11C11/412 ,  G11C11/418 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0629 ,  H01L27/092 ,  H01L27/1156 ,  H03K3/356182 ,  H03K19/0016

Abstract: To provide a semiconductor device that inhibits unexpected output of a high-level signal immediately after the rise of a power supply voltage. The semiconductor device includes a first buffer circuit, a level shifter circuit, and a second buffer circuit. A first potential is supplied to the first buffer circuit, and a second potential is supplied to the level shifter circuit and the second buffer circuit; consequently, the semiconductor device returns to a normal state. When the semiconductor device returns to a normal state, the second potential is supplied, so that the potential of a node in the level shifter circuit increases. To utilize the increase in the second potential or suppress malfunction due to the increase in the potential, capacitors are provided in the level shifter circuit. This inhibits unexpected operation of a transistor in the level shifter circuit.

公开(公告)号：US09754657B2

公开(公告)日：2017-09-05

申请号：US15153360

申请日：2016-05-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tatsuya Onuki ,  Yutaka Shionoiri

IPC: G11C11/24 ,  G11C11/409 ,  H01L29/786 ,  H01L27/12 ,  G11C11/56 ,  G11C11/404 ,  G11C11/4097 ,  H01L27/108 ,  H01L27/1156

CPC classification number: G11C11/409 ,  G11C11/24 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/56 ,  G11C11/565 ,  H01L27/10805 ,  H01L27/1156 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A novel semiconductor device, a semiconductor device capable of storing multi-level data, a semiconductor device with low power consumption, a semiconductor device with a reduced area, or a highly reliable semiconductor device is provided. The semiconductor device includes a memory cell which includes a first transistor and a capacitor, and a second transistor. The first transistor includes an oxide semiconductor in a channel formation region. One of a source and a drain of the first transistor is electrically connected to a first wiring. The other of the source and the drain of the first transistor is electrically connected to one of electrodes of the capacitor. The other of the electrodes of the capacitor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the first wiring.

公开(公告)号：US09653479B2

公开(公告)日：2017-05-16

申请号：US15072076

申请日：2016-03-16

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidekazu Miyairi ,  Yuichi Sato ,  Yuji Asano ,  Tetsunori Maruyama ,  Tatsuya Onuki ,  Shuhei Nagatsuka

IPC: H01L21/00 ,  H01L29/78 ,  H01L27/12 ,  H01L29/786 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L29/16

CPC classification number: H01L27/1225 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76885 ,  H01L21/8258 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/1207 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/16 ,  H01L29/45 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/7869 ,  H01L29/78696

Abstract: To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator.