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    CIRCUIT, SEMICONDUCTOR DEVICE, AND CLOCK TREE
    102.
    发明申请
    CIRCUIT, SEMICONDUCTOR DEVICE, AND CLOCK TREE 有权
    电路，半导体器件和时钟树

    公开(公告)号：US20150326225A1

    公开(公告)日：2015-11-12

    申请号：US14705619

    申请日：2015-05-06

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO

    IPC: H03K19/0185

    CPC classification number: H03K19/018521 ,  H01L27/0629 ,  H01L27/1225 ,  H01L29/045 ,  H01L29/24 ,  H03K3/012 ,  H03K19/0008 ,  H03K19/0013 ,  H03K19/0016

    Abstract: A circuit with a reduced leakage current is provided. A first transistor, a third transistor, and a second transistor are electrically connected in this order in series, a drain of the second transistor and a source of the third transistor are electrically connected to each other and are electrically connected to an output node. The first transistor is a p-channel transistor. The second and third transistors are n-channel transistors each including a semiconductor region including an oxide semiconductor. The third transistor functions as a switch that controls electrical connection between a drain of the first transistor and an output node of the circuit. In the standby mode, the third transistor is in an off state.

    Abstract translation: 提供了具有减小的漏电流的电路。 第一晶体管，第三晶体管和第二晶体管按此顺序电连接，第二晶体管的漏极和第三晶体管的源极彼此电连接并电连接到输出节点。 第一晶体管是p沟道晶体管。 第二和第三晶体管是n沟道晶体管，每个晶体管包括包括氧化物半导体的半导体区域。 第三晶体管用作控制第一晶体管的漏极和电路的输出节点之间的电连接的开关。 在待机模式下，第三晶体管处于断开状态。

    MEMORY DEVICE AND ELECTRONIC DEVICE
    104.
    发明申请
    MEMORY DEVICE AND ELECTRONIC DEVICE 审中-公开
    存储器件和电子器件

    公开(公告)号：US20150325282A1

    公开(公告)日：2015-11-12

    申请号：US14705698

    申请日：2015-05-06

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO ,  Tatsuya ONUKI

    IPC: G11C11/4096

    CPC classification number: G11C11/4096 ,  G11C11/4091 ,  G11C11/4097

    Abstract: To provide a memory device with low power consumption. The memory device includes a sense amplifier, bit lines, memory cells, and first transistors. The bit lines are provided over a layer where the sense amplifier is provided. The memory cells are provided over a layer where the bit lines are provided. The memory cell includes a second transistor and a capacitor. The sense amplifier and the bit lines are electrically connected to each other through the first transistors. The sense amplifier may include at least one layer of a conductor.

    Abstract translation: 提供具有低功耗的存储器件。 存储器件包括读出放大器，位线，存储单元和第一晶体管。 位线设置在提供读出放大器的层上。 存储单元被提供在提供位线的层上。 该存储单元包括第二晶体管和电容器。 读出放大器和位线通过第一晶体管彼此电连接。 读出放大器可以包括至少一层导体。

    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE HAVING THE SAME
    105.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE HAVING THE SAME 有权
    半导体存储器件和半导体器件和具有该半导体器件的电子器件

    公开(公告)号：US20150270270A1

    公开(公告)日：2015-09-24

    申请号：US14659714

    申请日：2015-03-17

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Kiyoshi KATO

    IPC: H01L27/108 ,  H01L29/786

    CPC classification number: H01L27/10897 ,  G11C11/403 ,  H01L27/10811 ,  H01L27/10894 ,  H01L27/1225 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

    Abstract: A memory cell includes a node and first transistor to third transistors. The third transistor and the second transistor are electrically connected to a fourth wiring and a third wiring in series, respectively. A gate of the third transistor is electrically connected to a second wiring. A gate of the second transistor is electrically connected to the node. In the first transistor, a gate is electrically connected to a first wiring, one of a source and a drain is electrically connected to the fourth wiring, and the other of the source and the drain is electrically connected to the node. The first transistor includes an oxide semiconductor layer where a channel is formed and a channel length and a channel width thereof are each shorter than 100 nm. A maximum potential of the first wiring is lower than or equal to 2 V.

    Abstract translation: 存储单元包括节点和第三晶体管至第三晶体管。 第三晶体管和第二晶体管分别电连接到第四布线和第三布线。 第三晶体管的栅极电连接到第二布线。 第二晶体管的栅极电连接到节点。 在第一晶体管中，栅极电连接到第一布线，源极和漏极中的一个电连接到第四布线，并且源极和漏极中的另一个电连接到节点。 第一晶体管包括其中形成沟道并且沟道长度和沟道宽度均小于100nm的氧化物半导体层。 第一布线的最大电位低于或等于2 V.

    SEMICONDUCTOR DEVICE
    106.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20150123183A1

    公开(公告)日：2015-05-07

    申请号：US14595692

    申请日：2015-01-13

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Kiyoshi KATO ,  Shuhei NAGATSUKA

    IPC: H01L27/11

    CPC classification number: H01L27/1108 ,  G11C16/0408 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1225 ,  H01L28/60

    Abstract: A semiconductor device with a novel structure is provided in which stored data can be held even when power is not supplied and the number of writing is not limited. The semiconductor includes a second transistor and a capacitor over a first transistor. The capacitor includes a source or drain electrode and a gate insulating layer of the second transistor and a capacitor electrode over an insulating layer which covers the second transistor. The gate electrode of the second transistor and the capacitor electrode overlap at least partly with each other with the insulating layer interposed therebetween. By forming the gate electrode of the second transistor and the capacitor electrode using different layers, an integration degree of the semiconductor device can be improved.

    Abstract translation: 提供具有新颖结构的半导体器件，其中即使在不提供电力并且写入次数不受限制的情况下，也可以保持存储的数据。 半导体在第一晶体管上包括第二晶体管和电容器。 电容器包括源极或漏极以及第二晶体管的栅极绝缘层，以及覆盖第二晶体管的绝缘层上的电容器电极。 第二晶体管的栅电极和电容器电极至少部分地彼此重叠，绝缘层位于它们之间。 通过使用不同层来形成第二晶体管的栅电极和电容电极，可以提高半导体器件的集成度。

    SEMICONDUCTOR DEVICE
    107.
    发明申请
    SEMICONDUCTOR DEVICE 审中-公开
    半导体器件

    公开(公告)号：US20150014685A1

    公开(公告)日：2015-01-15

    申请号：US14500445

    申请日：2014-09-29

    Applicant: Semiconductor Energy Laboratory Co., Ltd.

    Inventor： Toshihiko SAITO ,  Yuki HATA ,  Kiyoshi KATO

    IPC: H01L27/12

    CPC classification number: H01L27/124 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/12 ,  H01L27/1225 ,  H01L28/40

    Abstract: An object is to miniaturize a semiconductor device. Another object is to reduce the area of a driver circuit of a semiconductor device including a memory cell. The semiconductor device includes an element formation layer provided with at least a first semiconductor element, a first wiring provided over the element formation layer, an interlayer film provided over the first wiring, and a second wiring overlapping with the first wiring with the interlayer film provided therebetween. The first wiring, the interlayer film, and the second wiring are included in a second semiconductor element. The first wiring and the second wiring are wirings to which the same potentials are supplied.

    Abstract translation: 目的是使半导体器件小型化。 另一个目的是减小包括存储单元的半导体器件的驱动电路的面积。 半导体器件包括至少设置有第一半导体元件的元件形成层，设置在元件形成层上的第一布线，设置在第一布线上的中间膜，和与第一布线重叠的第二布线，设置有夹层膜 之间。 第一布线，层间膜和第二布线包括在第二半导体元件中。 第一布线和第二布线是提供相同电位的布线。

    SEMICONDUCTOR DEVICE
    109.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250133835A1

    公开(公告)日：2025-04-24

    申请号：US18965260

    申请日：2024-12-02

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Kiyoshi KATO

    IPC: H10D88/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  H10B12/00 ,  H10B41/20 ,  H10B41/30 ,  H10B41/70 ,  H10B99/00 ,  H10D86/00

    Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limit on the number of write operations. The semiconductor device includes a first memory cell including a first transistor and a second transistor, a second memory cell including a third transistor and a fourth transistor, and a driver circuit. The first transistor and the second transistor overlap at least partly with each other. The third transistor and the fourth transistor overlap at least partly with each other. The second memory cell is provided over the first memory cell. The first transistor includes a first semiconductor material. The second transistor, the third transistor, and the fourth transistor include a second semiconductor material.

    SEMICONDUCTOR DEVICE
    110.
    发明申请
    SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20250133824A1

    公开(公告)日：2025-04-24

    申请号：US18834712

    申请日：2023-01-27

    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

    Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Hitoshi KUNITAKE ,  Ryota HODO ,  Shunpei YAMAZAKI

    IPC: H10D86/40 ,  H10D30/67 ,  H10D64/68

    Abstract: A semiconductor device that can be miniaturized or highly integrated is provided. First to second transistors share a first metal oxide over a first insulator and a first conductor over the first metal oxide; the first transistor includes a second conductor and a second insulator which are over the first metal oxide and a third conductor over the second insulator; the second transistor includes a fourth conductor and a third insulator which are over the first metal oxide and a fifth conductor over the third insulator; a side surface of the first insulator includes a portion in contact with the fourth conductor; an end portion of the fourth conductor includes a portion positioned outward from an end portion of the first insulator; the second insulator is positioned between the first conductor and the second conductor; the metal oxide and the third conductor overlap with each other with the second insulator therebetween; the third insulator is positioned between the first conductor and the fourth conductor; and the metal oxide and the fifth conductor overlap with each other with the third insulator therebetween.

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