-
公开(公告)号：US10236068B2
公开(公告)日：2019-03-19
申请号：US15873872
申请日：2018-01-17
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu
Abstract: The present invention relates to an improved sensing amplifier and related method for use in read operations in flash memory devices. In one embodiment, a voltage offset is induced in the sensing amplifier through the use of capacitors.
-
公开(公告)号：US10199112B1
公开(公告)日：2019-02-05
申请号：US15687092
申请日：2017-08-25
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu , Stanley Hong
Abstract: Numerous embodiments for an improved sense amplifier circuit for reading data in a flash memory cell are disclosed. The embodiments each compare current or voltage measurements from a data block with a reference block to determine the value stored in the selected memory cell in the data block. The use of one or more localized boost circuits allow the embodiments to utilize lower operating voltages than prior art sense amplifier circuits, resulting in reduced power consumption.
-
公开(公告)号：US09985042B2
公开(公告)日：2018-05-29
申请号：US15489548
申请日：2017-04-17
Applicant: Silicon Storage Technology, Inc.
Inventor： Chien-Sheng Su , Jeng-Wei Yang , Man-Tang Wu , Chun-Ming Chen , Hieu Van Tran , Nhan Do
IPC: H01L21/306 , H01L21/8238 , H01L27/11568 , H01L21/3065
CPC classification number: H01L27/11568 , H01L21/30604 , H01L21/30625 , H01L21/3065 , H01L21/823821 , H01L28/00
Abstract: A method of forming a memory device with memory cells over a planar substrate surface and FinFET logic devices over fin shaped substrate surface portions, including forming a protective layer over previously formed floating gates, erase gates, word line poly and source regions in a memory cell portion of the substrate, then forming fins into the surface of the substrate and forming logic gates along the fins in a logic portion of the substrate, then removing the protective layer and completing formation of word line gates from the word line poly and drain regions in the memory cell portion of the substrate.
-
公开(公告)号：US09972630B2
公开(公告)日：2018-05-15
申请号：US15295022
申请日：2016-10-17
Applicant: Silicon Storage Technology, Inc.
Inventor： Chien-Sheng Su , Feng Zhou , Jeng-Wei Yang , Hieu Van Tran , Nhan Do
IPC: H01L21/336 , H01L27/11521 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/788 , H01L27/11524
CPC classification number: H01L27/11521 , H01L21/28273 , H01L27/11524 , H01L29/42328 , H01L29/66825 , H01L29/788 , H01L29/7881
Abstract: A memory device including a silicon substrate having a planar upper surface in a memory cell area and an upwardly extending silicon fin in a logic device area. The silicon fin includes side surfaces extending up and terminating at a top surface. The logic device includes spaced apart source and drain regions with a channel region extending there between (along the top surface and the side surfaces), and a conductive logic gate disposed over the top surface and laterally adjacent to the side surfaces. The memory cell includes spaced apart source and drain regions with a second channel region extending there between, a conductive floating gate disposed over one portion of the second channel region, a conductive word line gate disposed over another portion of the second channel region, a conductive control gate disposed over the floating gate, and a conductive erase gate disposed over the source region.
-
公开(公告)号：US09972493B2
公开(公告)日：2018-05-15
申请号：US15594883
申请日：2017-05-15
Applicant: Silicon Storage Technology, Inc.
Inventor： Chien-Sheng Su , Jeng-Wei Yang , Man-Tang Wu , Chun-Ming Chen , Hieu Van Tran , Nhan Do
IPC: H01L21/336 , H01L21/28 , H01L21/306 , G11C16/04 , H01L29/772 , H01L29/423
CPC classification number: H01L21/28 , G11C16/0425 , H01L21/28273 , H01L21/30604 , H01L27/11539 , H01L29/42328 , H01L29/772
Abstract: A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.
-
Patent Agency Ranking
公开(公告)号：US20180040482A1
公开(公告)日：2018-02-08
申请号：US15594883
申请日：2017-05-15
Applicant: Silicon Storage Technology, Inc.
Inventor： Chien-Sheng Su , Jeng-Wei Yang , Man-Tang Wu , Chun-Ming Chen , Hieu Van Tran , Nhan Do
IPC: H01L21/28 , H01L29/423 , H01L29/772 , H01L21/306 , G11C16/04
CPC classification number: H01L21/28 , G11C16/0425 , H01L21/28273 , H01L21/30604 , H01L27/11539 , H01L29/42328 , H01L29/772
Abstract: A method of forming a memory device that includes forming a first insulation layer on a semiconductor substrate, forming a conductive material layer on the first insulation layer, forming an insulation block on the conductive material layer, forming an insulation spacer along a side surface of the insulation block and on the conductive material layer, etching the conductive material layer to form a block of the conductive material disposed directly under the insulation block and the insulation spacer, removing the insulation spacer, forming a second insulation layer having a first portion wrapping around an exposed upper edge of the block of the conductive material and a second portion disposed on a first portion of the first insulation layer over the substrate, and forming a conductive block insulated from the block of the conductive material by the second insulation layer and from the substrate by the first and second insulation layers.
-
公开(公告)号：US20170337978A1
公开(公告)日：2017-11-23
申请号：US15158460
申请日：2016-05-18
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Anh Ly , Thuan Vu
CPC classification number: G11C16/3431 , G11C16/0425 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/28
Abstract: The present invention relates to a flash memory cell with only four terminals and decoder circuitry for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.
-
公开(公告)号：US20170337466A1
公开(公告)日：2017-11-23
申请号：US15594439
申请日：2017-05-12
Inventor： Farnood Merrikh Bayat , Xinjie Guo , Dmitri Strukov , Nhan Do , Hieu Van Tran , Vipin Tiwari , Mark Reiten
CPC classification number: G06N3/04 , G06F3/061 , G06F3/0655 , G06F3/0688 , G06N3/0454 , G06N3/063
Abstract: An artificial neural network device that utilizes one or more non-volatile memory arrays as the synapses. The synapses are configured to receive inputs and to generate therefrom outputs. Neurons are configured to receive the outputs. The synapses include a plurality of memory cells, wherein each of the memory cells includes spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate disposed over and insulated from a first portion of the channel region and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to a number of electrons on the floating gate. The plurality of memory cells are configured to multiply the inputs by the stored weight values to generate the outputs.
-
公开(公告)号：US09747986B2
公开(公告)日：2017-08-29
申请号：US15003811
申请日：2016-01-22
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Hung Quoc Nguyen , Anh Ly , Thuan Vu
CPC classification number: G11C16/08 , G06F17/5081 , G11C7/062 , G11C8/10 , G11C11/1673 , G11C13/004 , G11C16/26 , G11C16/28
Abstract: Improved PMOS and NMOS transistor designs for sensing circuitry use in advanced nanometer flash memory devices are disclosed.
-
110.发明授权公开(公告)号：US09634018B2
公开(公告)日：2017-04-25
申请号：US15050309
申请日：2016-02-22
Applicant: Silicon Storage Technology, Inc.
Inventor： Chien-Sheng Su , Jeng-Wei Yang , Man-Tang Wu , Chun-Ming Chen , Hieu Van Tran , Nhan Do
IPC: H01L29/788 , H01L27/11521 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/78 , H01L27/105 , H01L27/11551
CPC classification number: H01L27/11521 , H01L21/28273 , H01L27/1052 , H01L27/11551 , H01L29/0847 , H01L29/42328 , H01L29/66795 , H01L29/66818 , H01L29/66825 , H01L29/785 , H01L29/7856 , H01L29/7881
Abstract: A non-volatile memory cell including a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.
-
-
-
-
-
-
-
-
-
Search Results
355
records
(took 0.026 seconds)
