公开(公告)号：US20160093576A1

公开(公告)日：2016-03-31

申请号：US14837604

申请日：2015-08-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chih-Hsien Chiu ,  Hao-Ju Fang ,  Hsin-Lung Chung ,  Cho-Hsin Chang ,  Tsung-Hsien Tsai ,  Chia-Yang Chen ,  Chun-Chi Ke

IPC: H01L23/552 ,  H01L23/31 ,  H01L21/54 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/498 ,  H01L23/16

CPC classification number: H01L23/552 ,  H01L21/4853 ,  H01L21/54 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/16 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49838 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A semiconductor package is provided, including: a substrate having opposing first and second surfaces; a plurality of semiconductor components disposed on and electrically connected to the first surface; an encapsulant encapsulating the first surface and the semiconductor components and having at least one first groove that partitions the substrate into a plurality of package units, each of which has at least one of the semiconductor components; and a metal layer formed on the substrate and the encapsulant and encapsulating a periphery of the package units, with the second surface exposed from the metal layer, wherein the metal layer is formed along a wall surface of the first groove, to form a second groove corresponding in position to the first groove and having a metal surface. Therefore, the package units are isolated and form a multilayer isolated structure, including metal layers and air layers, and are electromagnetically shielded from one another.

Abstract translation: 提供一种半导体封装，包括：具有相对的第一和第二表面的衬底; 设置在第一表面上并电连接到第一表面的多个半导体部件; 密封剂，其封装所述第一表面和所述半导体部件，并且具有将所述基板分隔成多个封装单元的至少一个第一凹槽，所述多个封装单元具有至少一个所述半导体部件; 以及金属层，形成在所述基板和所述密封剂上并且封装所述封装单元的周边，其中所述第二表面从所述金属层露出，其中所述金属层沿着所述第一凹槽的壁表面形成，以形成第二凹槽 对应于第一凹槽的位置并且具有金属表面。 因此，封装单元被隔离并且形成包括金属层和空气层的多层隔离结构，并且彼此电磁屏蔽。

公开(公告)号：US20150340248A1

公开(公告)日：2015-11-26

申请号：US14817624

申请日：2015-08-04

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Tsung-Hsien Tsai ,  Chih-Hsien Chiu ,  Hsin-Lung Chung ,  Chien-Cheng Lin

IPC: H01L21/48 ,  H01L21/78 ,  H01L21/56

CPC classification number: H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/97 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2224/19 ,  H01L2224/82 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A package having ESD (electrostatic discharge) and EMI (electromagnetic interference) preventing functions includes: a substrate unit having a ground structure and an I/O structure disposed therein; at least a semiconductor component disposed on a surface of the substrate unit and electrically connected to the ground structure and the I/O structure; an encapsulant covering the surface of the substrate unit and the semiconductor component; and a metal layer disposed on exposed surfaces of the encapsulant and side surfaces of the substrate unit and electrically insulated from the ground structure, thereby protecting the semiconductor component against ESD and EMI so as to improve the product yield and reduce the risk of short circuits.

Abstract translation: 具有ESD（静电放电）和EMI（电磁干扰）防止功能的封装包括：具有接地结构和设置在其中的I / O结构的衬底单元; 至少一个半导体部件，设置在所述基板单元的表面上并电连接到所述接地结构和所述I / O结构; 覆盖所述基板单元和所述半导体部件的表面的密封剂; 以及金属层，其设置在基板单元的密封剂和侧表面的暴露表面上并与基底结构电绝缘，从而保护半导体部件免受ESD和EMI，从而提高产品产量并降低短路的风险。

公开(公告)号：US20150123251A1

公开(公告)日：2015-05-07

申请号：US14133842

申请日：2013-12-19

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD

Inventor： Chih-Hsien Chiu ,  Chia-Yang Chen ,  Tsung-Hsien Tsai ,  Heng-Cheng Chu ,  Cheng-Yu Chiang

IPC: H01L23/552 ,  H01L23/31

CPC classification number: H01L23/552 ,  H01L23/31 ,  H01L23/3121 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/3011 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package is disclosed, which includes: a packaging structure having at least a semiconductor element; and at least three shielding layers sequentially stacked on the packaging structure so as to cover the semiconductor element, wherein a middle layer of the shielding layers is lower in electrical conductivity than adjacent shielding layers on both sides of the middle layer, thereby reducing electromagnetic interferences so as to increase the shielding effectiveness.

Abstract translation: 公开了一种半导体封装，其包括：具有至少半导体元件的封装结构; 以及至少三个屏蔽层，其顺序堆叠在所述封装结构上以覆盖所述半导体元件，其中所述屏蔽层的中间层的导电性低于所述中间层的两侧上的相邻屏蔽层，从而降低电磁干扰 以提高屏蔽效能。

公开(公告)号：US20140203395A1

公开(公告)日：2014-07-24

申请号：US14087554

申请日：2013-11-22

Applicant: Siliconware Precision industries Co., Ltd

Inventor： Tsung-Hsien Tsai ,  Heng-Cheng Chu ,  Chien-Cheng Lin ,  Chih-Hsien Chiu ,  Hsin-Lung Chung ,  Yude Chu

IPC: H01L27/06 ,  H01L49/02

CPC classification number: H01L23/66 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/64 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L25/16 ,  H01L25/50 ,  H01L28/00 ,  H01L2223/6661 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19105 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a method of manufacturing the same are provided. The semiconductor package includes: a substrate having a plurality of conductive lands and a plurality of bonding pads surrounding the conductive lands formed on a surface thereof; a plurality of passive devices mounted on the conductive lands; an insulation layer formed on the surface and having a portion of the passive devices embedded therein; a semiconductor chip mounted on a top surface of the insulation layer; a plurality of bonding wires electrically connecting the semiconductor chip and the bonding pads; an encapsulant formed on the surface of the substrate to encapsulate the insulation layer, the bonding wires and the semiconductor chip, wherein a region of the semiconductor chip projected onto the substrate covers a portion of an outermost one of the passive devices. Therefore, the mounting density of the passive devices is improved.

Abstract translation: 提供半导体封装及其制造方法。 半导体封装包括：具有多个导电焊盘的衬底和围绕形成在其表面上的导电焊盘的多个焊盘; 安装在导电焊盘上的多个无源器件; 绝缘层，其形成在所述表面上并且具有嵌入其中的无源器件的一部分; 安装在所述绝缘层的顶表面上的半导体芯片; 电连接半导体芯片和接合焊盘的多个接合线; 形成在基板的表面上以封装绝缘层，接合线和半导体芯片的密封剂，其中投射到基板上的半导体芯片的区域覆盖无源器件中最外面的一个的一部分。 因此，无源器件的安装密度提高。

公开(公告)号：US20140080265A1

公开(公告)日：2014-03-20

申请号：US14086135

申请日：2013-11-21

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD

Inventor： Ching-Hua Chen ,  Heng-Cheng Chu ,  Hsin-Lung Chung ,  Chih-Hsien Chiu ,  Chia-Yang Chen

IPC: H01L21/56

CPC classification number: H01L21/56 ,  H01L21/6835 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/49174 ,  H01L2224/73265 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A carrier-free semiconductor package includes a circuit structure having an insulating layer and a circuit layer embedded in the insulating layer and having a plurality of conductive traces and RF (radio frequency) traces, a chip disposed on a first surface of the insulating layer and electrically connected to the conductive traces, an encapsulant covering the chip and the circuit layer, a ground layer formed on a second surface of the insulating layer opposite to the first surface, and a plurality of solder balls disposed on the conductive traces or terminals on the conductive traces, wherein portions of the solder balls electrically connect the ground layer so as to allow the RF traces and the ground layer to form a microstrip line having an RF function, thus obtaining a single-layer carrier-free semiconductor package having low cost and simplified RF design.

Abstract translation: 一种无载体半导体封装，包括具有绝缘层和嵌入绝缘层中的电路层并具有多个导电迹线和RF（射频）迹线的电路结构，设置在该绝缘层的第一表面上的芯片，以及 电连接到导电迹线，覆盖芯片和电路层的密封剂，形成在与第一表面相对的绝缘层的第二表面上的接地层和设置在导电迹线上的多个焊球 导电迹线，其中焊球的部分电连接接地层，以便允许RF迹线和接地层形成具有RF功能的微带线，从而获得具有低成本的单层无载流子半导体封装， 简化射频设计。