公开(公告)号：US20190198666A1

公开(公告)日：2019-06-27

申请号：US15850854

申请日：2017-12-21

Applicant: Texas Instruments Incorporated

Inventor： Sunglyong Kim ,  Seetharaman Sridhar ,  Sameer Pendharkar

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/49 ,  H01L29/66 ,  H01L21/761 ,  H01L21/28 ,  H03K17/687

Abstract: A lateral junction diode device includes a substrate having at least a semiconductor surface layer. A depletion-mode LDMOS device is in the semiconductor surface layer including a source, drain, and a gate above a gate dielectric, and a channel region under the gate on the gate dielectric. A drift region is between the channel region and the drain, wherein the drain also provides a cathode for the lateral junction diode device. An embedded diode includes a second cathode and an anode that is shared with the device. The embedded diode is junction isolated by an isolation region located between the anode and the source. The anode and isolation region are directly connected to the gate and the second cathode is directly connected to the source.

公开(公告)号：US10312095B1

公开(公告)日：2019-06-04

申请号：US16163602

申请日：2018-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Dong Seup Lee ,  Yoshikazu Kondo ,  Pinghai Hao ,  Sameer Pendharkar

IPC: H01L29/205 ,  H01L21/28 ,  H01L29/423 ,  H01L21/02 ,  H01L29/778 ,  H01L29/51 ,  H01L29/66 ,  H01L29/20

Abstract: An electronic device, that in various embodiments includes a first semiconductor layer comprising a first group III nitride. A second semiconductor layer is located directly on the first semiconductor layer and comprises a second different group III nitride. A cap layer comprising the first group III nitride is located directly on the second semiconductor layer. A dielectric layer is located over the cap layer and directly contacts the second semiconductor layer through an opening in the cap layer.

公开(公告)号：US10290699B2

公开(公告)日：2019-05-14

申请号：US15245511

申请日：2016-08-24

Applicant: Texas Instruments Incorporated

Inventor： Hideaki Kawahara ,  Binghua Hu ,  Sameer Pendharkar

IPC: H01L49/02 ,  H01L21/283 ,  H01L21/311 ,  H01L21/768 ,  H01L23/535

Abstract: An integrated trench capacitor and method for making the trench capacitor is disclosed. The method includes forming a trench in a silicon layer, forming a first dielectric on the exposed surface of the trench, performing an anisotropic etch of the first dielectric to expose silicon at the bottom of the trench, implanting a dopant into exposed silicon at the bottom of the trench, forming a first polysilicon layer over the first dielectric, forming a second dielectric over the first polysilicon layer, and forming a second polysilicon layer over the second dielectric to fill the trench.

公开(公告)号：US20180175191A1

公开(公告)日：2018-06-21

申请号：US15830263

申请日：2017-12-04

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Ming-yeh Chuang

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/40 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/408 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/66689

Abstract: A power transistor is provided with at least one transistor finger that lies within a semiconductor material. The gate oxide is segmented into a set of segments with thick field oxide between each segment in order to reduce gate capacitance and thereby improve a resistance times gate charge figure of merit.

公开(公告)号：US09882041B1

公开(公告)日：2018-01-30

申请号：US15353857

申请日：2016-11-17

Applicant: Texas Instruments Incorporated

Inventor： Jungwoo Joh ,  Naveen Tipirneni ,  Chang Soo Suh ,  Sameer Pendharkar

IPC: H01L29/20 ,  H01L29/778 ,  H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/308

CPC classification number: H01L29/7786 ,  H01L21/2654 ,  H01L21/266 ,  H01L21/3083 ,  H01L29/0646 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/0843 ,  H01L29/2003 ,  H01L29/41758 ,  H01L29/66462

Abstract: A High Electron Mobility Transistor (HEMT) includes an active layer on a substrate, and a Group IIIA-N barrier layer on the active layer. An isolation region is through the barrier layer to provide at least one isolated active area including the barrier layer on the active layer. A gate is over the barrier layer. A drain includes at least one drain finger including a fingertip having a drain contact extending into the barrier layer to contact to the active layer and a source having a source contact extending into the barrier layer to contact to the active layer. The source forms a loop that encircles the drain. The isolation region includes a portion positioned between the source and drain contact so that there is a conduction barrier in a length direction between the drain contact of the fingertip and the source.

公开(公告)号：US09831320B2

公开(公告)日：2017-11-28

申请号：US15013412

申请日：2016-02-02

Applicant: Texas Instruments Incorporated

Inventor： Philip Leland Hower ,  Sameer Pendharkar ,  Marie Denison

IPC: H01L29/66 ,  H01L21/336 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L21/266 ,  H01L27/088 ,  H01L21/225

CPC classification number: H01L29/66681 ,  H01L21/2253 ,  H01L21/266 ,  H01L27/088 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0634 ,  H01L29/0642 ,  H01L29/0646 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.

公开(公告)号：US09812439B2

公开(公告)日：2017-11-07

申请号：US14514066

申请日：2014-10-14

Applicant: Texas Instruments Incorporated

Inventor： Timothy Patrick Pauletti ,  Sameer Pendharkar ,  Wayne Tien-Feng Chen ,  Jonathan Brodsky ,  Robert Steinhoff

IPC: H02H9/04 ,  H01L27/02 ,  H01L29/74 ,  H01L29/87 ,  H01L29/749

CPC classification number: H01L27/0262 ,  H01L29/7436 ,  H01L29/749 ,  H01L29/87 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

公开(公告)号：US09786665B1

公开(公告)日：2017-10-10

申请号：US15238198

申请日：2016-08-16

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Binghua Hu ,  Alexei Sadovnikov ,  Guru Mathur

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/76229 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L29/0615 ,  H01L29/0649

Abstract: A semiconductor device adopts an isolation scheme to protect low voltage transistors from high voltage operations. The semiconductor device includes a substrate, a buried layer, a transistor well region, a first trench, and a second trench. The substrate has a top surface and a bottom surface. The buried layer is positioned within the substrate, and the transistor well region is positioned above the buried layer. The first trench extends from the top surface to penetrate the buried layer, and the first trench has a first trench depth. The second trench extending from the top surface to penetrate the buried layer. The second trench is interposed between the first trench and the transistor well region. The second trench has a second trench depth that is less than the first trench depth.

公开(公告)号：US09660021B1

公开(公告)日：2017-05-23

申请号：US15403403

申请日：2017-01-11

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L21/823487 ,  H01L29/063 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/51 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66734 ,  H01L29/7809

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US09608105B2

公开(公告)日：2017-03-28

申请号：US14730748

申请日：2015-06-04

Applicant: Texas Instruments Incorporated

Inventor： Takehito Tamura ,  Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/06 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

Abstract: The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.