公开(公告)号：US20190035450A1

公开(公告)日：2019-01-31

申请号：US16151388

申请日：2018-10-04

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G11C11/24 ,  G04F10/10

Abstract: A reading circuit for a charge-retention circuit stage is provided with a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The reading circuit further has an operational amplifier having a first input terminal that is coupled to the floating node and receives a reading voltage, a second input terminal receives a reference voltage, and an output terminal on which it supplies an output voltage, the value of which is a function of the comparison between the reading voltage and the reference voltage and indicative of a residual charge in the storage capacitor. A shifting stage shifts the value of the reading voltage of the floating node, before the comparison is made between the reading voltage and the reference voltage for supplying the output voltage.

公开(公告)号：US10193009B1

公开(公告)日：2019-01-29

申请号：US15945972

申请日：2018-04-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy

IPC: H01L31/113 ,  H01L31/0224 ,  H01L27/146

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

公开(公告)号：US20190018191A1

公开(公告)日：2019-01-17

申请号：US16133064

申请日：2018-09-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Guerber ,  Charles Baudot ,  Florian Domengie

IPC: G02B6/122 ,  G02B6/43 ,  G02B6/30 ,  G02B6/26 ,  G02B6/14 ,  G02B6/138 ,  G02B6/13 ,  G02B6/126 ,  G02B6/12

Abstract: A photonic integrated circuit includes an optical coupling device situated between two successive interconnection metal levels. The optical coupling device includes a first optical portion that receives an optical signal having a transverse electric component in a fundamental mode and a transverse magnetic component. A second optical portion converts the transverse magnetic component of the optical signal into a converted transverse electric component in a higher order mode. A third optical portion separates the transverse electric component from the converted transverse electric component and switches the higher order mode to the fundamental mode. A fourth optical portion transmits the transverse electric component to one waveguide and transmits the converted transverse electric component to another waveguide.

公开(公告)号：US10162048B2

公开(公告)日：2018-12-25

申请号：US15392032

申请日：2016-12-28

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Boris Rodrigues ,  Marie Guillon ,  Yvon Cazaux ,  Benoit Giffard

IPC: G01S7/48 ,  H01L27/146 ,  H04N5/374 ,  G01S7/491 ,  G01S7/486

Abstract: A pixel is formed on a semiconductor substrate that includes a photosensitive area having a first doped layer and a charge collection area of a first conductivity type extending through at least part of the first doped layer. At least two charge storage areas, each including a well of the first conductivity type, are separated from the charge collection area at least by a first portion of the first layer. The first portion is covered by a first gate. Each charge storage area is laterally delimited by two insulated conductive electrodes. A second doped layer of the second conductivity type covers the charge collection area and the charge storage areas.

公开(公告)号：US10161830B2

公开(公告)日：2018-12-25

申请号：US15460425

申请日：2017-03-16

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Patrick Le Maitre ,  Jean-Francois Carpentier

IPC: G01M11/00 ,  H04B10/07

Abstract: An intermediate signal is separated into a first sub-signal and a second sub-signal according to a separation coefficient having a known real value. The first sub-signal is delivered to a first photonic circuit containing at least one photonic device to be characterized and a first photonic part. The second sub-signal is delivered to a second photonic circuit containing a second photonic part having a same transfer function as the first photonic part but lacking the at least one photonic device. Optical output signals from the first and second photonic circuits are converted into first and second electrical signals. Losses of the at least one photonic device are determined from processing the electrical signals and from the known real value of the separation coefficient.

公开(公告)号：US20180331136A1

公开(公告)日：2018-11-15

申请号：US15926491

申请日：2018-03-20

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Axel Crocherie ,  Etienne Mortini ,  Jean Luc Huguenin

IPC: H01L27/146

CPC classification number: H01L27/1464 ,  H01L27/14603 ,  H01L27/1462 ,  H01L27/14623 ,  H01L27/14629 ,  H01L27/14636 ,  H01L27/14643

Abstract: The invention relates to an image sensor and method for reducing image defects. A photoconversion area is formed in a semiconductor layer. An insulating layer formed over the semiconductor layer contains a metal element. A lens over the insulting layer is positioned opposite the photoconversion area to focus light on it. A layer of light-absorbing material is deposited on the side of the metal element facing the lens to prevent reflection of parasitic light rays within the image device.

公开(公告)号：US20180330998A1

公开(公告)日：2018-11-15

申请号：US15973969

申请日：2018-05-08

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Loic GABEN

IPC: H01L21/84 ,  H01L21/225 ,  H01L21/02 ,  H01L21/311 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12

CPC classification number: H01L21/845 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/2254 ,  H01L21/31111 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78696

Abstract: A strip or portions of a strip of silicon-germanium is made by first producing a strip of silicon suspended above a substrate. At least a portion of the strip of silicon is with a layer of silicon-germanium. Germanium enrichment of the portion of the strip of silicon is accomplished through a thermal oxidation. The resulting silicon oxide formed during the thermal oxidation is then removed.

公开(公告)号：US10126497B2

公开(公告)日：2018-11-13

申请号：US15377848

申请日：2016-12-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Frederic Boeuf ,  Charles Baudot

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/126 ,  G02B6/27

Abstract: A three-dimensional photonic integrated structure includes a first semiconductor substrate and a second semiconductor substrate. The first substrate incorporates a first waveguide and the second semiconductor substrate incorporates a second waveguide. An intermediate region located between the two substrates is formed by a one dielectric layer. The second substrate further includes an optical coupler configured for receiving a light signal. The first substrate and dielectric layer form a reflective element located below and opposite the grating coupler in order to reflect at least one part of the light signal.

公开(公告)号：US20180323228A1

公开(公告)日：2018-11-08

申请号：US16031710

申请日：2018-07-10

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois Roy ,  Philippe Are

IPC: H01L27/146 ,  H01L27/148

CPC classification number: H01L27/14607 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14614 ,  H01L27/1463 ,  H01L27/14636 ,  H01L27/14638 ,  H01L27/14643 ,  H01L27/14812

Abstract: An image sensor includes a control circuit and pixels. Each pixel includes: a photosensitive area, a substantially rectangular storage area adjacent to the photosensitive area, and a read area. First and second insulated vertical electrodes electrically connected to each other are positioned opposite each other and delimit the storage area. The first electrode extends between the storage area and the photosensitive area. The second electrode includes a bent extension opposite a first end of the first electrode, with the storage area emerging onto the photosensitive area on the side of the first end. The control circuit operates to apply a first voltage to the first and second electrodes to perform a charge transfer, and a second voltage to block charge transfer.

公开(公告)号：US20180323196A1

公开(公告)日：2018-11-08

申请号：US16038705

申请日：2018-07-18

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS

Inventor： Florian Cacho ,  Vincent Huard

IPC: H01L27/092 ,  H03K19/21 ,  H03K19/094 ,  H03K19/003 ,  G01R31/317 ,  H01L29/10 ,  H03K3/037 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  G01R31/31725 ,  H01L21/823892 ,  H01L29/1083 ,  H03K3/037 ,  H03K19/00315 ,  H03K19/094 ,  H03K19/21

Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.