公开(公告)号：US20240105545A1

公开(公告)日：2024-03-28

申请号：US17934346

申请日：2022-09-22

Applicant: Apple Inc.

Inventor： Jiongxin Lu ,  Kunzhong Hu ,  Jun Zhai ,  Sanjay Dabral

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L23/3738 ,  H01L23/3185 ,  H01L24/08 ,  H01L24/29 ,  H01L24/32 ,  H01L25/18 ,  H01L24/05 ,  H01L24/80 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29124 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/32245 ,  H01L2224/32503 ,  H01L2224/80379

Abstract: Semiconductor packages including an integrated heat spreader and methods of fabrication are described. In an embodiment, a semiconductor package includes a first package level, a second package level including one or more second-level chiplets, and a heat spreader bonded to the second package level with a metallic layer, which may include one or more intermetallic compounds formed by transient liquid phase bonding.

公开(公告)号：US20240038689A1

公开(公告)日：2024-02-01

申请号：US18485709

申请日：2023-10-12

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/58 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/564 ,  H01L23/585 ,  H01L23/544 ,  H01L2223/5446

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：US11824015B2

公开(公告)日：2023-11-21

申请号：US17397834

申请日：2021-08-09

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Sanjay Dabral ,  SivaChandra Jangam ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L23/00 ,  H01L21/78 ,  H01L23/58 ,  H01L23/544

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/544 ,  H01L23/564 ,  H01L23/585 ,  H01L2223/5446

Abstract: Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.

公开(公告)号：US20230317624A1

公开(公告)日：2023-10-05

申请号：US18058991

申请日：2022-11-28

Applicant: Apple Inc.

Inventor： Wei Chen ,  Yi Xu ,  Jie-Hua Zhao ,  Jun Zhai

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48225

Abstract: Microelectronic packages and methods of fabrication are described. In an embodiment, a redistribution layer spans across multiple components, and includes a region of patterned wiring traces that may mitigate stress in the RDL between the multiple components.

公开(公告)号：US11699949B2

公开(公告)日：2023-07-11

申请号：US17383983

申请日：2021-07-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  David A. Secker ,  Jun Zhai ,  Ralf M. Schmitt ,  Vidhya Ramachandran ,  Wenjie Mao

IPC: H02M3/07 ,  G05F3/10 ,  H01L29/66 ,  H01L23/00 ,  H01L23/522

CPC classification number: H02M3/07 ,  G05F3/10 ,  H01L23/5223 ,  H01L23/5227 ,  H01L24/17 ,  H01L29/66181 ,  H01L2224/02379

Abstract: Power management systems are described. In an embodiment, a power management system includes a voltage source, a circuit load located within a chip, and a switched capacitor voltage regulator (SCVR) coupled to voltage source and the circuit load to receive an input voltage from the voltage source and supply an output voltage to the circuit load. The SCVR may include circuitry located within the chip and a discrete integrated passive device (IPD) connected to the chip.

公开(公告)号：US20230154897A1

公开(公告)日：2023-05-18

申请号：US18156287

申请日：2023-01-18

Applicant: Apple Inc.

Inventor： Chonghua Zhong ,  Jun Zhai ,  Kunzhong Hu

IPC: H01L25/065 ,  H01L23/24 ,  H01L23/538 ,  H01L23/00 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/24 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/08 ,  H01L24/16 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08225 ,  H01L2224/16225 ,  H01L2224/24155 ,  H01L2224/24226 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: Package structure with folded die arrangements and methods of fabrication are described. In an embodiment, a package structure includes a first die and vertical interposer side-by-side. A second die is face down on an electrically connected with the vertical interposer, and a local interposer electrically connects the first die with the vertical interposer.

公开(公告)号：US11646302B2

公开(公告)日：2023-05-09

申请号：US17013279

申请日：2020-09-04

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai ,  Po-Hao Chang ,  Hsien-Che Lin ,  Ying-Chieh Ke ,  Kunzhong Hu

IPC: H01L25/18 ,  H01L23/24

CPC classification number: H01L25/18 ,  H01L23/24

Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

公开(公告)号：US20230017445A1

公开(公告)日：2023-01-19

申请号：US17815893

申请日：2022-07-28

Applicant: Apple Inc.

Inventor： Kunzhong Hu ,  Chonghua Zhong ,  Jiongxin Lu ,  Jun Zhai

IPC: H01L23/14 ,  H01L25/065 ,  H01L23/28 ,  H01L23/00 ,  H01L21/56 ,  H01L23/488

Abstract: Electronic packages and methods of formation are described in which an interposer is solderlessly connected with a package substrate. The interposer may be stacked on the package substrate and joined with a conductive film, and may be formed on the package substrate during a reconstitution sequence.

公开(公告)号：US11532563B2

公开(公告)日：2022-12-20

申请号：US17026708

申请日：2020-09-21

Applicant: Apple Inc.

Inventor： Karthik Shanmugam ,  Jun Zhai ,  Rajasekaran Swaminathan

IPC: H01L23/538 ,  H01L23/31 ,  H05K1/18 ,  H01L21/56 ,  H01L25/16

Abstract: Packages and packaging techniques are described in which a patterned carrier substrate can be used to create a reconstituted fanout substrate with a topography that can accommodate components of different thicknesses. In an embodiment, a wiring layer is formed directly on a multiple level topography of a molding compound layer including embedded components.

公开(公告)号：US20220199517A1

公开(公告)日：2022-06-23

申请号：US17133096

申请日：2020-12-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Jun Zhai ,  Kunzhong Hu ,  Raymundo M. Camenforte

IPC: H01L23/528 ,  H01L23/58 ,  H01L25/18 ,  H01L23/00

Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.