公开(公告)号：US20130334630A1

公开(公告)日：2013-12-19

申请号：US13527173

申请日：2012-06-19

申请人： Witold Kula ,  Gurtej S. Sandhu ,  Stephen J. Kramer

发明人： Witold Kula ,  Gurtej S. Sandhu ,  Stephen J. Kramer

IPC分类号： H01L29/82 ,  H01L21/8246

CPC分类号： H01L43/08 ,  G11C11/161 ,  H01L27/228 ,  H01L43/02 ,  H01L43/12

摘要： Methods of forming magnetic memory cells are disclosed. Magnetic and non-magnetic materials are formed into a primal precursor structure in an initial stress state of essentially no strain, compressive strain, or tensile strain. A stress-compensating material, e.g., a non-sacrificial, conductive material, is formed to be disposed on the primal precursor structure to form a stress-compensated precursor structure in a net beneficial stress state. Thereafter, the stress-compensated precursor structure may be patterned to form a cell core of a memory cell. The net beneficial stress state of the stress-compensated precursor structure lends to formation of one or more magnetic regions, in the cell core, exhibiting a vertical magnetic orientation without deteriorating a magnetic strength of the one or more magnetic regions. Also disclosed are memory cells, memory cell structures, semiconductor device structures, and spin torque transfer magnetic random access memory (STT-MRAM) systems.

摘要翻译： 公开了形成磁存储器单元的方法。 磁性和非磁性材料在基本上没有应变，压缩应变或拉伸应变的初始应力状态下形成原始前体结构。 形成应力补偿材料，例如非牺牲导电材料，以设置在原始前体结构上以在净有益应力状态下形成应力补偿前体结构。 此后，应力补偿前体结构可以被图案化以形成存储单元的单元芯。 应力补偿前体结构的净有益应力状态有助于在电池芯中形成一个或多个磁性区域，呈现垂直磁性取向而不会使一个或多个磁性区域的磁强度恶化。 还公开了存储器单元，存储单元结构，半导体器件结构和自旋转矩传递磁随机存取存储器（STT-MRAM）系统。

公开(公告)号：US08564039B2

公开(公告)日：2013-10-22

申请号：US12755940

申请日：2010-04-07

申请人： Gurtej S. Sandhu

发明人： Gurtej S. Sandhu

IPC分类号： H01L29/78 ,  H01L29/82

CPC分类号： H01L27/22 ,  G11C11/161 ,  G11C11/221 ,  G11C11/223 ,  H01L27/1052 ,  H01L27/11517 ,  H01L27/228 ,  H01L28/55 ,  H01L29/49 ,  H01L29/78 ,  H01L29/7841 ,  H01L29/78696 ,  H01L29/82 ,  H01L43/14

摘要： Semiconductor devices include a transistor having a gate structure located close to a channel region that comprises a colossal magnetocapacitive material. The gate structure is configured to affect electrical current flow through the channel region between a source and a drain. The colossal magnetocapacitive material optionally may be disposed between two structures, one or both of which may be electrically conductive, magnetic, or both electrically conductive and magnetic. Methods of fabricating semiconductor devices include forming a colossal magnetocapacitive material close to a channel region between a source and a drain of a transistor, and configuring the colossal magnetocapacitive material to exhibit colossal magnetocapacitance for generating an electrical field in the channel region. Methods of affecting current flow through a transistor include causing a colossal magnetocapacitive material to exhibit colossal magnetocapacitance and generate an electrical field in a channel region of a transistor.

摘要翻译： 半导体器件包括晶体管，其晶体管具有靠近包括巨大的磁电容材料的沟道区域的栅极结构。 栅极结构被配置为影响通过源极和漏极之间的沟道区域的电流。 巨大的磁电容材料任选地可以设置在两个结构之间，其中一个或两个可以是导电的，磁的或者是导电的和磁的。 制造半导体器件的方法包括在晶体管的源极和漏极之间形成接近于沟道区域的巨大的磁电容材料，并且配置巨大的磁电容材料以显示用于在沟道区域中产生电场的巨大的磁电容。 影响通过晶体管的电流的方法包括使巨大的磁电容材料显示出巨大的磁电容并在晶体管的沟道区域中产生电场。

公开(公告)号：US20130248797A1

公开(公告)日：2013-09-26

申请号：US13427529

申请日：2012-03-22

申请人： Gurtej S. Sandhu ,  Scott E. Sills

发明人： Gurtej S. Sandhu ,  Scott E. Sills

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L45/16 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148

摘要： Some embodiments include methods of forming memory cells. An opening is formed over a first conductive structure to expose an upper surface of the first conductive structure. The opening has a bottom level with a bottom width. The opening has a second level over the bottom level, with the second level having a second width which is greater than the bottom width. The bottom level of the opening is filled with a first portion of a multi-portion programmable material, and the second level is lined with the first portion. The lined second level is filled with a second portion of the multi-portion programmable material. A second conductive structure is formed over the second portion. Some embodiments include memory cells.

摘要翻译： 一些实施例包括形成存储器单元的方法。 在第一导电结构上形成开口以暴露第一导电结构的上表面。 开口具有底部底部宽度。 开口具有超过底部水平的第二水平，其中第二水平具有大于底部宽度的第二宽度。 开口的底部水平填充有多部分可编程材料的第一部分，并且第二层与第一部分相衬。 衬里的第二层被多部分可编程材料的第二部分填充。 在第二部分上形成第二导电结构。 一些实施例包括存储器单元。

公开(公告)号：US08524561B2

公开(公告)日：2013-09-03

申请号：US13248625

申请日：2011-09-29

申请人： Gurtej S. Sandhu ,  Mark Kiehlbauch

发明人： Gurtej S. Sandhu ,  Mark Kiehlbauch

IPC分类号： H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/823456

摘要： A method of forming a plurality of transistor gates having at least two different work functions includes forming first and second transistor gates over a substrate having different widths, with the first width being narrower than the second width. A material is deposited over the substrate including over the first and second gates. Within an etch chamber, the material is etched from over both the first and second gates to expose conductive material of the first gate and to reduce thickness of the material received over the second gate yet leave the second gate covered by the material. In situ within the etch chamber after the etching, the substrate is subjected to a plasma comprising a metal at a substrate temperature of at least 300° C. to diffuse said metal into the first gate to modify work function of the first gate as compared to work function of the second gate.

摘要翻译： 形成具有至少两个不同功函数的多个晶体管栅极的方法包括在具有不同宽度的衬底上形成第一和第二晶体管栅极，第一宽度窄于第二宽度。 材料沉积在包括第一和第二栅极上的衬底上。 在蚀刻室内，从第一和第二栅极上方蚀刻材料以暴露第一栅极的导电材料并且减小在第二栅极上接收的材料的厚度，但是离开由材料覆盖的第二栅极。 在蚀刻之后的蚀刻室内的原位，使衬底在至少300℃的衬底温度下经受包含金属的等离子体，以将所述金属扩散到第一栅极中以改变第一栅极的功函数，与 第二门的功能。

公开(公告)号：US20130193400A1

公开(公告)日：2013-08-01

申请号：US13359715

申请日：2012-01-27

申请人： Gurtej S. Sandhu ,  John K. Zahurak

发明人： Gurtej S. Sandhu ,  John K. Zahurak

IPC分类号： H01L45/00

CPC分类号： H01L27/2454 ,  H01L27/2463 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147

摘要： Some embodiments include memory cell structures. The structures include a vertical transistor having a bottom source/drain region electrically coupled to a first access/sense line, and having a gate comprised by a second access/sense line. The structures also include programmable material over the vertical transistor and electrically coupled with a top source/drain region of the vertical transistor, with the programmable material having at least two compositionally different regions. The structures also include an electrically conductive material over and directly against the programmable material. Some embodiments include memory arrays.

摘要翻译： 一些实施例包括存储器单元结构。 该结构包括垂直晶体管，其具有电耦合到第一存取/感测线的底部源极/漏极区域，并且具有包括第二存取/感测线的栅极。 结构还包括垂直晶体管上的可编程材料，并与垂直晶体管的顶部源极/漏极区域电耦合，可编程材料具有至少两个组成不同的区域。 该结构还包括导电材料，并且可直接抵靠可编程材料。 一些实施例包括存储器阵列。

公开(公告)号：US20130187117A1

公开(公告)日：2013-07-25

申请号：US13355382

申请日：2012-01-20

申请人： Gurtej S. Sandhu ,  Bhaskar Srinivasan

发明人： Gurtej S. Sandhu ,  Bhaskar Srinivasan

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L45/08 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1608

摘要： Some embodiments include memory cells which contain, in order; a first electrode material, a first metal oxide material, a second metal oxide material, and a second electrode material. The first metal oxide material has at least two regions which differ in oxygen concentration relative to one another. One of the regions is a first region and another is a second region. The first region is closer to the first electrode material than the second region, and has a greater oxygen concentration than the second region. The second metal oxide material includes a different metal than the first metal oxide material. Some embodiments include methods of forming memory cells in which oxygen is substantially irreversibly transferred from a region of a metal oxide material to an oxygen-sink material. The oxygen transfer creates a difference in oxygen concentration within one region of the metal oxide material relative to another.

公开(公告)号：US08411477B2

公开(公告)日：2013-04-02

申请号：US12765606

申请日：2010-04-22

申请人： Sanh D. Tang ,  Gurtej S. Sandhu

发明人： Sanh D. Tang ,  Gurtej S. Sandhu

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C11/00 ,  H01L21/82

CPC分类号： G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C7/18 ,  G11C11/4097 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2213/71 ,  G11C2213/78 ,  H01L27/0688 ,  H01L27/101

摘要： An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extensions extend through multiple of the tiers. Individual of the memory cells comprise multi-resistive state material received between one of the horizontally oriented word lines and one of the local vertical bit line extensions where such cross, with such ones comprising opposing conductive electrodes of individual memory cells where such cross. A plurality of bit line select circuits individually electrically and physically connects to individual of the local vertical bit line extensions and are configured to supply a voltage potential to an individual of the global horizontal bit lines. Other embodiments and aspects are disclosed.

公开(公告)号：US08394683B2

公开(公告)日：2013-03-12

申请号：US12014508

申请日：2008-01-15

申请人： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

发明人： D. V. Nirmal Ramaswamy ,  Gurtej S. Sandhu

IPC分类号： H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L21/8239 ,  H01L27/0738 ,  H01L27/11524 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/42328 ,  H01L29/42348 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

摘要： Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.

摘要翻译： 一些实施例包括形成半导体结构的方法。 可以形成n型掺杂材料和p型掺杂材料的交替层。 交替层可以被图案化成通过开口彼此间隔开的多个垂直柱。 开口可以衬有隧道电介质，电荷储存材料和阻挡电介质。 绝缘材料和导电控制栅极材料的交替层可以形成在衬里的开口内。 一些实施例包括形成NAND单元电池的方法。 可以形成交替的n型材料和p型材料的柱。 柱可以衬有隧道电介质层，电荷存储材料层和阻挡电介质层。 可以在排列的柱之间形成绝缘材料和导电控制栅极材料的交替层。 一些实施例包括半导体结构，并且一些实施例包括NAND单元单元。

公开(公告)号：US08394682B2

公开(公告)日：2013-03-12

申请号：US13191192

申请日：2011-07-26

申请人： Gurtej S. Sandhu

发明人： Gurtej S. Sandhu

IPC分类号： H01L21/82

CPC分类号： H01L21/768 ,  H01L23/525 ,  H01L23/53276 ,  H01L29/0665 ,  H01L29/0676 ,  H01L29/1606 ,  H01L29/66022 ,  H01L29/66742 ,  H01L29/7788 ,  H01L29/78642 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

摘要： Some embodiments include methods of forming graphene-containing switches. A bottom electrode may be formed over a base, and a first electrically conductive structure may be formed to extend upwardly from the bottom electrode. Dielectric material may be formed along a sidewall of the first electrically conductive structure, while leaving a portion of the bottom electrode exposed. A graphene structure may be formed to be electrically coupled with the exposed portion of the bottom electrode. A second electrically conductive structure may be formed on an opposing side of the graphene structure from the first electrically conductive structure. A top electrode may be formed over the graphene structure and electrically coupled with the second electrically conductive structure. The first and second electrically conductive structures may be configured to provide an electric field across the graphene structure.

公开(公告)号：US08361328B2

公开(公告)日：2013-01-29

申请号：US13276150

申请日：2011-10-18

申请人： Gurtej S. Sandhu

发明人： Gurtej S. Sandhu

IPC分类号： C02F1/68

CPC分类号： B01D21/262 ,  B01D43/00 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/172 ,  Y10S977/745 ,  Y10S977/746 ,  Y10S977/845 ,  Y10S977/847

摘要： A nanotube separation method includes depositing a tag on a nanotube in a nanotube mixture. The nanotube has a defect and the tag deposits at the defect where a deposition rate is greater than on another nanotube in the mixture lacking the defect. The method includes removing the tagged nanotube from the mixture by using the tag. As one option, the tag may contain a ferromagnetic material and the removing may include applying a magnetic field. As another option, the tag may contain an ionic material and the removing may include applying an electric field. As a further option, the tag may contain an atom having an atomic mass greater than the atomic mass of carbon and the removing may include applying a centrifugal force to the nanotube mixture. Any two or more of the indicated removal techniques may be combined.