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    Bitline control in differential magnetic memory
    112.
    发明授权
    Bitline control in differential magnetic memory 有权

    公开(公告)号：US10446213B1

    公开(公告)日：2019-10-15

    申请号：US15980977

    申请日：2018-05-16

    Applicant: Everspin Technologies Inc.

    Inventor： Yaojun Zhang ,  Syed M. Alam ,  Thomas Andre

    IPC: G11C11/00 ,  G11C11/16

    Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory includes a first memory cell, a first access circuit, a second access circuit, and a current generating circuit. The first memory cell includes a first magnetic tunnel junction and a second magnetic tunnel junction. The first access circuit is configured to receive access command signals for accessing the first magnetic tunnel junction. The first access circuit includes a first access switch and a second access switch. The second access circuit is configured to receive access command signals for accessing the second magnetic tunnel junction. The second access circuit includes a third access switch and a fourth access switch. The current generating circuit is configured to generate a first write current through the first magnetic tunnel junction and generate a second write current through the second magnetic tunnel junction based on data input signals.

    ECC word configuration for system-level ECC compatibility
    113.
    发明授权
    ECC word configuration for system-level ECC compatibility 有权

    公开(公告)号：US10256840B2

    公开(公告)日：2019-04-09

    申请号：US15385130

    申请日：2016-12-20

    Applicant: Everspin Technologies, Inc.

    Inventor： Syed M. Alam ,  Thomas Andre

    IPC: H03M13/00 ,  H03M13/29 ,  G06F11/10

    Abstract: A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page. The memory device is configurable to perform a first level of error correction on each of the ECC words associated with the page. A system-level error correction circuit is configurable to perform a second level of error correction on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device is configurable to provide only one bit of data per ECC word to an external source during an access from an external source.

    Tamper detection and response in a memory device
    116.
    发明授权
    Tamper detection and response in a memory device 有权
    存储设备中的防篡改检测和响应

    公开(公告)号：US09569640B2

    公开(公告)日：2017-02-14

    申请号：US14832495

    申请日：2015-08-21

    Applicant: Everspin Technologies, Inc.

    Inventor： Chitra K. Subramanian ,  Halbert S. Lin ,  Syed M. Alam ,  Thomas Andre

    IPC: G11C11/00 ,  G11C5/14 ,  G06F21/79 ,  G11C7/24 ,  G11C11/16 ,  G06F21/60 ,  G11C13/00

    CPC classification number: G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

    Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations, generating a mock current to emulate current expected during normal operation, and erasing data stored on the memory device.

    Abstract translation: 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。 当执行篡改检测检查时，使用检测存储单元的参考位与当前状态之间的比较来确定检测存储单元中的任何一个是否已经从其初始预定状态改变状态。 基于该比较，如果确定了阈值变化水平，则标记篡改检测指示。 一旦检测到篡改尝试，在存储器装置上的响应包括禁用一个或多个存储器操作，产生模拟电流以模拟在正常操作期间预期的电流，以及擦除存储在存储器件上的数据。

    Magnetic memory having two transistors and two magnetic tunnel junctions per memory cell
    119.
    发明授权
    Magnetic memory having two transistors and two magnetic tunnel junctions per memory cell 有权
    每个存储单元具有两个晶体管和两个磁性隧道结的磁存储器

    公开(公告)号：US09472256B1

    公开(公告)日：2016-10-18

    申请号：US14872678

    申请日：2015-10-01

    Applicant: Everspin Technologies, Inc.

    Inventor： Thomas Andre

    IPC: G11C11/16

    CPC classification number: G11C11/16 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    Abstract: Circuits and methods for driving generating multiple word line voltages used for writing to two-transistor two-magnetic tunnel junction (2T2MTJ) spin-torque magnetic random access memory (MRAM) cells. Some embodiments include auto-booting isolated word lines using common lines such as bit and source lines that are capacitively coupled to the word lines. Different memory architectures for 2T2MTJ memory arrays are also presented that include read/write circuits and word line drivers.

    Abstract translation: 用于驱动产生用于写入双晶体管双磁性隧道结（2T2MTJ）自旋转矩磁随机存取存储器（MRAM）单元的多个字线电压的电路和方法。 一些实施例包括使用诸如电容耦合到字线的位线和源极线的公共线自动引导隔离字线。 还提供了用于2T2MTJ存储器阵列的不同存储器架构，其中包括读/写电路和字线驱动器。

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