公开(公告)号：US20150333080A1

公开(公告)日：2015-11-19

申请号：US14741528

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ricardo Pablo Mikalo ,  Stefan Flachowsky

IPC: H01L27/115 ,  H01L29/49 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/045 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括掺杂有第一导电性确定杂质的半导体衬底。 半导体衬底在其中形成有掺杂有与第一导电率确定杂质不同的第二导电率确定杂质的第一阱，形成在第一阱内的第二阱，并且掺杂有第一导电率确定杂质，以及 第三阱与第一阱和第二阱间隔开并掺杂有第一导电性确定杂质。 集成电路还包括形成在半导体衬底上的浮栅结构。 浮置栅极结构包括设置在第二阱上并与第二阱分离的第一栅极元件，其具有电介质层，第二栅极元件设置在第三阱上并与第三阱与介电层分离，并且导电 连接器。

公开(公告)号：US09190516B2

公开(公告)日：2015-11-17

申请号：US14186387

申请日：2014-02-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Stefan Flachowsky ,  Alban Zaka ,  Jan Hoentschel

IPC: H01L29/78 ,  H01L29/161 ,  H01L29/08 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/3065 ,  H01L29/167 ,  H01L29/417 ,  H01L21/8234

CPC classification number: H01L29/7848 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/3065 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823425 ,  H01L29/045 ,  H01L29/0843 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/41725 ,  H01L29/66477 ,  H01L29/66636

Abstract: A methodology for forming a compressive strain layer with increased thickness that exhibits improved device performance and the resulting device are disclosed. Embodiments may include forming a recess in a source or drain region of a substrate, implanting a high-dose impurity in a surface of the recess, and depositing a silicon-germanium (SiGe) layer in the recess.

Abstract translation: 公开了一种用于形成具有提高的器件性能的具有增加的厚度的压缩应变层的方法以及所得到的器件。 实施例可以包括在衬底的源极或漏极区域中形成凹陷，在凹部的表面中注入高剂量杂质，以及在凹部中沉积硅 - 锗（SiGe）层。

公开(公告)号：US09165840B2

公开(公告)日：2015-10-20

申请号：US14579255

申请日：2014-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Matthias Kessler ,  Jan Hoentschel

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L27/12 ,  H01L27/06 ,  H01L21/8234 ,  H01L29/94 ,  H01L27/088

CPC classification number: H01L21/84 ,  H01L21/02428 ,  H01L21/76283 ,  H01L21/823412 ,  H01L21/823878 ,  H01L27/0629 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66181 ,  H01L29/7786 ,  H01L29/78 ,  H01L29/861 ,  H01L29/945

Abstract: A structure comprises a semiconductor substrate, a semiconductor-on-insulator region and a bulk region. The semiconductor-on-insulator region comprises a first semiconductor region, a dielectric layer provided between the semiconductor substrate and the first semiconductor region, and a first transistor comprising an active region provided in the first semiconductor region. The dielectric layer provides electrical isolation between the first semiconductor region and the semiconductor substrate. The bulk region comprises a second semiconductor region provided directly on the semiconductor substrate.

Abstract translation: 一种结构包括半导体衬底，绝缘体上半导体区域和体区域。 绝缘体上半导体区域包括第一半导体区域，设置在半导体衬底和第一半导体区域之间的电介质层，以及包括设置在第一半导体区域中的有源区的第一晶体管。 电介质层在第一半导体区域和半导体衬底之间提供电隔离。 本体区域包括直接设置在半导体衬底上的第二半导体区域。

公开(公告)号：US20150162414A1

公开(公告)日：2015-06-11

申请号：US14097338

申请日：2013-12-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Elke Erben

IPC: H01L29/49 ,  H01L29/51

CPC classification number: H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/7833

Abstract: When forming field effect transistors, a common problem is the formation of a Schottky barrier at the interface between a metal thin film in the gate electrode and a semiconductor material, typically polysilicon, formed thereupon. Fully silicided gates are known in the state of the art which may overcome this problem. The claimed method proposes an improved fully silicided gate achieved by forming a gate structure including an additional metal layer between the metal gate layer and the gate semiconductor material. A silicidation process can then be optimized so as to form a lower metal silicide layer comprising the metal of the additional metal layer and an upper metal silicide layer forming an interface with the lower metal silicide layer.

Abstract translation: 当形成场效应晶体管时，常见的问题是在栅电极中的金属薄膜与其上形成的半导体材料（通常为多晶硅）之间的界面处形成肖特基势垒。 完全硅化的门在现有技术中是已知的，这可以克服这个问题。 所要求保护的方法提出了通过在金属栅极层和栅极半导体材料之间形成包括附加金属层的栅极结构而实现的改进的全硅化栅。 然后可以优化硅化工艺，以便形成包含附加金属层的金属和形成与下金属硅化物层的界面的上金属硅化物层的下金属硅化物层。

公开(公告)号：US20150129966A1

公开(公告)日：2015-05-14

申请号：US14600097

申请日：2015-01-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/41783 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696

Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.

Abstract translation: 半导体结构包括衬底和晶体管。 晶体管包括设置在衬底上方的升高的源极区域和升高的漏极区域，一个或多个细长半导体管线，栅极电极和栅极绝缘层。 所述一个或多个细长半导体线连接在所述升高的源极区域和所述隆起的漏极区域之间，其中所述一个或多个细长半导体线路中的每一个的纵向方向基本上沿着垂直于所述衬底的厚度方向的水平方向延伸 。 每个细长半导体线包括沟道区。 栅电极围绕一个或多个细长半导体线路的每个沟道区域延伸。 栅极绝缘层设置在一个或多个细长半导体线路和栅电极中的每一个之间。

公开(公告)号：US08916928B2

公开(公告)日：2014-12-23

申请号：US14039450

申请日：2013-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/78 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886

Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

Abstract translation: 当在共同的制造顺序中形成复杂的多栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得 多个栅极晶体管和平面晶体管的阈值电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

公开(公告)号：US08835255B2

公开(公告)日：2014-09-16

申请号：US13747907

申请日：2013-01-23

Applicant: Globalfoundries Inc.

Inventor： Tim Baldauf ,  Stefan Flachowsky ,  Tom Hermann ,  Ralf Illgen

IPC: H01L21/336

CPC classification number: H01L29/66666 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/775

Abstract: A method comprises providing a semiconductor structure comprising a substrate and a nanowire above the substrate. The nanowire comprises a first semiconductor material and extends in a vertical direction of the substrate. A material layer is formed above the substrate. The material layer annularly encloses the nanowire. A first part of the nanowire is selectively removed relative to the material layer. A second part of the nanowire is not removed. A distal end of the second part of the nanowire distal from the substrate is closer to the substrate than a surface of the material layer so that the semiconductor structure has a recess at the location of the nanowire. The distal end of the nanowire is exposed at the bottom of the recess. The recess is filled with a second semiconductor material. The second semiconductor material is differently doped than the first semiconductor material.

Abstract translation: 一种方法包括提供包括衬底和衬底上方的纳米线的半导体结构。 纳米线包括第一半导体材料并沿着衬底的垂直方向延伸。 在衬底上形成材料层。 材料层环绕着纳米线。 相对于材料层选择性地去除纳米线的第一部分。 纳米线的第二部分不会被删除。 远离衬底的纳米线的第二部分的远端比材料层的表面更靠近衬底，使得半导体结构在纳米线的位置具有凹陷。 纳米线的远端暴露在凹槽的底部。 凹部填充有第二半导体材料。 第二半导体材料与第一半导体材料不同地掺杂。

公开(公告)号：US20140256135A1

公开(公告)日：2014-09-11

申请号：US13792540

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Peter Javorka ,  Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/308

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor.

Abstract translation: 本文公开的一种说明性方法包括以下步骤：形成覆盖P型晶体管并暴露N型晶体管的至少栅极帽层的掩模层，通过掩模层执行第一蚀刻工艺以去除部分 N型晶体管的栅极帽，从而限定了用于N型晶体管的减小厚度的栅极盖层，去除掩模层，并对P型晶体管和N型晶体管执行公共的第二蚀刻工艺 其去除了N型晶体管的P型晶体管的栅极盖层和减小厚度的栅极盖。

公开(公告)号：US20140252429A1

公开(公告)日：2014-09-11

申请号：US13792730

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.

Abstract translation: 提供了形成半导体器件的方法。 在一个实施例中，提供了一种在栅极绝缘层上形成栅极绝缘层和栅电极结构的栅极结构。 所述方法提供了沿着平行于连接源极和漏极的方向延伸的方向，相对于栅极绝缘层减小栅电极结构的尺寸。 提供一种具有栅极结构的半导体器件结构，该栅极结构包括形成在栅极绝缘层上方的栅极绝缘层和栅电极结构，其中栅电极结构的尺寸沿着基本上平行于源极方向的方向延伸 漏极相对于栅极绝缘层的尺寸减小。 根据一些示例，提供具有栅极硅长度的栅极结构，其与由栅极结构引起的沟道宽度解耦。

公开(公告)号：US20140248749A1

公开(公告)日：2014-09-04

申请号：US13783685

申请日：2013-03-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Nicolas Sassiat ,  Ralf Richter

IPC: H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7847

Abstract: A method comprises providing a semiconductor structure comprising a gate structure provided over a semiconductor region. An ion implantation process is performed. In the ion implantation process, a first portion of the semiconductor region adjacent the gate structure and a second portion of the semiconductor region adjacent the gate structure are amorphized so that a first amorphized region and a second amorphized region are formed adjacent the gate structure. An atomic layer deposition process is performed. The atomic layer deposition process deposits a layer of a material having an intrinsic stress over the semiconductor structure. A temperature at which at least a part of the atomic layer deposition process is performed and a duration of the at least a part of the atomic layer deposition process are selected such that the first amorphized region and the second amorphized region are re-crystallized during the atomic layer deposition process.

Abstract translation: 一种方法包括提供包括设置在半导体区域上的栅极结构的半导体结构。 进行离子注入工艺。 在离子注入工艺中，与栅极结构相邻的半导体区域的第一部分和与栅极结构相邻的半导体区域的第二部分是非晶化的，从而在栅极结构附近形成第一非晶化区域和第二非晶化区域。 进行原子层沉积工艺。 原子层沉积工艺在半导体结构上沉积具有固有应力的材料层。 进行原子层沉积工艺的至少一部分的温度，并且选择原子层沉积工艺的至少一部分的持续时间，使得第一非晶化区域和第二非晶化区域在 原子层沉积工艺。