摘要:
A system and method for sampling a data stream generates a number of clock signals having equally spaced phases and then samples a data stream using the clock signals. The clock phases are preferably based on a predetermined fraction of a data rate frequency of the data stream, and sampling is performed based on predetermined combinations of the clock signals. While the system and method is suitable for sampling data transmitted for a wide variety of data rates, the system and method is especially well-suited to sampling at data transmitted at high rates, for example, equal to or greater than 20 Gb/s.
摘要:
A transimpedance amplifier having a first input port to connect to a signal source having an output impedance, and a second input port loaded by an impedance matched to the output impedance of the signal source, the amplifier comprising three stage pairs. The first stage pair comprises two inverting amplifiers, each employing negative feedback. The second stage pair comprises two inverting amplifiers with cross-coupled negative feedback. The third stage pair is similar in structure to the first stage pair. The inverter amplifiers in the third stage pair provide the differential voltage.
摘要:
A method and apparatus for optical signaling. In one embodiment, a laser driver converts a digital voltage sequence to a current signal having a bias mode adjustable by a bias control and a modulation mode adjustable by a modulation control. A laser generates an optical signal responsive to the current signal of the laser driver. In one embodiment, a photo-detector receives an optical signal and generates a single ended current signal. A transimpedance amplifier circuit converts the single ended current signal to a differential voltage signal. A clock recovery circuit generates an aligned clock signal and a sampler circuit uses the aligned clock signal to retrieve a digital voltage sequence.
摘要:
According to some embodiments, a circuit includes a delay stage of a ring oscillator. The delay stage may include a first differential pair, a second differential pair, and a third differential pair. The first differential pair may be coupled to a first current-steering circuit, receive a differential input signal, and output a first differential signal. The second differential pair may receive the differential input signal and output a second differential signal, and the third differential pair may be coupled to a second current-steering circuit, receive the second differential signal from the second differential pair, and output the first differential signal. An amount of delay between the differential input signal and the first differential signal is based on relative amounts of current steered by the first current-steering circuit and the second current-steering circuit.
摘要:
A laser driver for high speed interconnections may convert a digital signal to a current train of a bias mode to represent logical zero and of a modulation mode to represent logical one. An optical signal thus produced may include an optical offset. An optical receiver may include a photo-detector to receive the optical signal and generate a current signal, which includes a corresponding current offset. A first amplifier stage converts the current signal to a voltage signal and a second amplifier stage generates a digital output from the voltage signal. One or more low-pass filters may be used to filter the digital output and generate a filtered offset signal for a differential amplifier to generate an offset cancellation signal. The offset cancellation signal may be provided to offset cancellation circuitry to remove the current offset from the current signal generated by the photo-detector.
摘要:
Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
摘要:
A voltage dependent capacitor to provide soft error rate tolerance in an integrated circuit is disclosed. In one embodiment, a parallel n-p voltage dependent capacitor is used to protect a node from noise. In another embodiment, an nFET-in-nWell voltage dependent capacitor is used to provide a soft error rate tolerant capacitor with reduced area.
摘要:
In some embodiments, the invention involves a die having a first conductor carrying a power supply voltage and a second conductor carrying a ground voltage. A semiconductor capacitor operating in depletion mode is coupled between the first and second conductors to provide decoupling capacitance between the first and second conductors, the semiconductor capacitor having a gate voltage. Various configurations may be used including: n+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and n+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in an n-body; p+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and p+ source/drain regions in a p-body; n+ gate poly and n+ source/drain regions in a p-body. The power supply voltage may have a larger absolute value than does a flatband voltage.