公开(公告)号：US20240371729A1

公开(公告)日：2024-11-07

申请号：US18312613

申请日：2023-05-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Biswanath Senapati ,  David Wolpert ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger ,  Leon Sigal ,  Brent A. Anderson ,  Albert M. Chu ,  Reinaldo Vega

IPC: H01L23/48 ,  H01L29/417

Abstract: A semiconductor structure including a gate contact above and in direct contact with a top surface of a gate. a backside wiring layer below a backside power delivery network. and a contact via extending between the gate contact and the backside wiring layer.

公开(公告)号：US20240363524A1

公开(公告)日：2024-10-31

申请号：US18306267

申请日：2023-04-25

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Nicholas Anthony Lanzillo ,  Brent A. Anderson ,  Lawrence A. Clevenger ,  Albert M. Chu ,  Reinaldo Vega ,  Ruilong Xie

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/7684

Abstract: Embodiments of present invention provide an interconnect structure. The structure includes a metal line embedded in a dielectric layer; a first via intersecting with the metal line; and a second via intersecting with the metal line, the second via being horizontally separated from the first via by a length that is less than a blech length of the metal line, where the first and the second via extend vertically at least from a top surface of the metal line to a bottom surface of the metal line and have a width that is equal to or large than a width of the metal line. One or more method of forming the same are also provided.

公开(公告)号：US20240321879A1

公开(公告)日：2024-09-26

申请号：US18188042

申请日：2023-03-22

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Ruilong Xie ,  Albert M. Chu ,  Nicholas Anthony Lanzillo ,  Reinaldo Vega

IPC: H01L27/088 ,  H01L21/8234 ,  H01L23/48 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823475 ,  H01L23/481 ,  H01L29/41791 ,  H01L29/7851

Abstract: Semiconductor devices and methods of forming the same include a first layer including lower colinear vertical transfer field effect transistors (VTFETs). At least two of the colinear first VTFETs have a first shared bottom source/drain structure. A second layer is positioned over the first layer and includes upper colinear VTFETs. At least two of the upper colinear VTFETs have a second shared bottom source/drain structure.

公开(公告)号：US20240213244A1

公开(公告)日：2024-06-27

申请号：US18145059

申请日：2022-12-22

Applicant: International Business Machines Corporation

Inventor： Brent A. Anderson ,  Albert M. Chu ,  Ruilong Xie ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Reinaldo Vega

IPC: H01L27/092 ,  H01L21/8238 ,  H01L23/528 ,  H01L29/08 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L27/092 ,  H01L21/823871 ,  H01L21/823885 ,  H01L23/5286 ,  H01L29/0847 ,  H01L29/41741 ,  H01L29/7827

Abstract: Embodiments of the invention provide a multi-layer integrated circuit (IC) structure that includes a cell having a cell boundary defined by a plurality of transistor-gate pitch (TGP) regions and an in-line contact region. The plurality of TGP regions include a reduced-area TGP region and non-reduced area TGP regions. The reduced-area TGP region is less than each of the non-reduced-area TGP regions. An in-line contact is within the in-line contact region and operable to electrically couple to a source or drain (S/D) region within the in-line contact region.

公开(公告)号：US20240203996A1

公开(公告)日：2024-06-20

申请号：US18067148

申请日：2022-12-16

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Lawrence A. Clevenger ,  Nicholas Anthony Lanzillo ,  Albert M. Chu ,  Reinaldo Vega ,  Brent A. Anderson

IPC: H01L27/118 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L23/5286 ,  H01L27/0207 ,  H01L2027/11816 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: Embodiments of the invention provide a multi-layer integrated circuit (IC) structure that includes a back-end-of-line (BEOL) region at a first side of a wafer. A backside region is at a second side of the wafer that is opposite the first side of the wafer. A set of signal lines are in the BEOL region, and a set of power rails are in the backside region. The set of signal lines includes a substantially constant signal-line pitch between each signal line in the set of signal lines. The set of power rails includes a substantially varying power-rail pitch between each power rail in the set of power rails.

公开(公告)号：US20240194681A1

公开(公告)日：2024-06-13

申请号：US18079079

申请日：2022-12-12

Applicant: International Business Machines Corporation

Inventor： Albert M. Chu ,  Brent A. Anderson ,  Nicholas Anthony Lanzillo ,  Reinaldo Vega ,  Lawrence A. Clevenger ,  Ruilong Xie

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11822 ,  H01L2027/11881

Abstract: A semiconductor structure comprising a first circuit row and a second circuit row adjacent the first circuit row. The first circuit row comprises a first circuit cell and a second circuit cell, the first circuit cell having a first cell height greater than a first row height of the first circuit row, the second circuit cell having a second cell height different than the first cell height. The second circuit row comprises a third circuit cell, the third circuit cell having a third cell height less than a second row height of the second circuit row. The first circuit cell in the first circuit row is at least partially aligned with the third circuit cell in the second circuit row.

公开(公告)号：US20240194236A1

公开(公告)日：2024-06-13

申请号：US18065195

申请日：2022-12-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Takashi Ando ,  Reinaldo Vega ,  David Wolpert ,  Nicholas Anthony Lanzillo

IPC: G11C11/22 ,  H10B53/30

CPC classification number: G11C11/221 ,  G11C11/2273 ,  H01L27/11507 ,  H01L28/65 ,  H01L28/75

Abstract: A capacitive memory cell includes an electrode, a tunneling barrier layer in direct contact with the electrode, a charge trapping layer in direct contact with the tunneling barrier layer, a ferroelectric layer in direct contact with the charge trapping layer, and another electrode in direct contact with the ferroelectric layer.

公开(公告)号：US20240186245A1

公开(公告)日：2024-06-06

申请号：US18061602

申请日：2022-12-05

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Kisik Choi ,  Reinaldo Vega ,  Albert M. Chu ,  Nicholas Anthony Lanzillo ,  Lawrence A. Clevenger

IPC: H01L23/528 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: One or more systems, devices, and/or methods of fabrication provided herein relate to reduced parasitic capacitance of power via bars. According to one embodiment, a semiconductor device can comprise a field-effect transistor (FET), and a power via bar coupled to a backside power rail, wherein the power via bar has greater height adjacent to a source and drain region of the field-effect transistor (FET) relative to a gate of the FET to mitigates parasitic capacitance within the device.

公开(公告)号：US11990470B2

公开(公告)日：2024-05-21

申请号：US17483958

申请日：2021-09-24

Applicant: International Business Machines Corporation

Inventor： Takashi Ando ,  Reinaldo Vega ,  Cheng Chi ,  Praneet Adusumilli

IPC: H01L27/08 ,  H01L49/02

CPC classification number: H01L27/0805 ,  H01L28/60

Abstract: An apparatus includes a first plate, a second plate, a third plate, a ferroelectric dielectric, and a paraelectric dielectric. The ferroelectric dielectric is between the first plate and the second plate such that the first plate, the ferroelectric dielectric, and the second plate form a first capacitor. The paraelectric dielectric is between the second plate and the third plate such that the second plate, the paraelectric dielectric, and the third plate form a second capacitor.

公开(公告)号：US20240145238A1

公开(公告)日：2024-05-02

申请号：US18050554

申请日：2022-10-28

Applicant: International Business Machines Corporation

Inventor： Reinaldo Vega ,  Shogo Mochizuki ,  Ruilong Xie ,  Julien Frougier ,  Ravikumar Ramachandran

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L21/0251 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/775

Abstract: Embodiments of the invention include an isolation layer under a nanosheet stack of a transistor and a graded layer under the isolation layer. The graded layer includes an impurity gradient.