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    RECONFIGURABLE MEMORY SYSTEM DATA STROBES
    113.
    发明申请
    RECONFIGURABLE MEMORY SYSTEM DATA STROBES 有权
    可重构存储器系统数据条

    公开(公告)号：US20150023118A1

    公开(公告)日：2015-01-22

    申请号：US14509572

    申请日：2014-10-08

    Applicant: RAMBUS INC.

    Inventor： Ian Shaeffer ,  Frederick Ware ,  Craig E. Hampel

    IPC: G06F3/06 ,  G11C7/22

    CPC classification number: G06F3/0634 ,  G06F3/0665 ,  G06F3/0689 ,  G06F13/1694 ,  G06F2212/262 ,  G11C7/22

    Abstract: In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of the components of the differential data strobe may be used as a timing reference for a first portion of the set of data signals and the other component used as a timing reference for a second portion of the set of data signals. Different data mask-related schemes also may be invoked for different modes of operation. For example, in a first mode of operation a memory controller may generate a data mask signal to prevent a portion of a set of data from being written to a memory array. Then, in a second mode of operation the memory controller may invoke a coded value replacement scheme or a data strobe transition inhibition scheme to prevent a portion of a set of data from being written to a memory array.

    Abstract translation: 在可重新配置的基于数据选通的存储器系统中，数据选通可以在不同的操作模式下重新安排。 例如，在一种操作模式中，差分数据选通可以用作给定的一组数据信号的定时参考。 在第二操作模式中，可以将差分数据选通的一个组件用作数据信号组的第一部分的定时参考，另一组件用作该组数据信号的第二部分的定时参考 数据信号。 也可以针对不同的操作模式调用不同的数据掩码相关方案。 例如，在第一操作模式中，存储器控制器可以生成数据掩码信号以防止一组数据被写入存储器阵列。 然后，在第二操作模式中，存储器控制器可以调用编码值替换方案或数据选通转换禁止方案，以防止一组数据被写入存储器阵列。

    METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULES
    114.
    发明申请
    METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULES 有权
    用于同步在线程存储器模块中的地址和控制信号的方法和系统

    公开(公告)号：US20150019786A1

    公开(公告)日：2015-01-15

    申请号：US14284473

    申请日：2014-05-22

    Applicant: RAMBUS INC.

    Inventor： Arun Vaidyanath ,  Craig E. Hampel

    IPC: G06F13/16 ,  G06F12/06

    CPC classification number: G06F13/16 ,  G06F12/06 ,  G06F13/1689 ,  G06F2212/251 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1072 ,  G11C8/18 ,  G11C29/023 ,  G11C29/025 ,  G11C29/027

    Abstract: A memory system includes a memory module which further includes a set of memory devices. The set of memory devices includes a first subset of memory devices and a second subset of memory devices. An address bus is disposed on the memory module, wherein the address bus includes a first segment coupled to the first subset and a second segment coupled to the second subset. An address signal traverses the set of memory devices in sequence. The memory system also includes a memory controller which is coupled to the memory module. The memory controller includes a first circuit to output a first control signal that controls the first subset, such that the first control signal and the address signal arrive at a memory device in the first subset at substantially the same time. The memory controller additionally includes a second circuit to output a second control signal that controls the second subset, such that the second control signal and the address signal arrive at a memory device in the second subset at substantially the same time.

    Abstract translation: 存储器系统包括还包括一组存储器件的存储器模块。 该组存储器件包括存储器件的第一子集和存储器件的第二子集。 地址总线设置在存储器模块上，其中地址总线包括耦合到第一子集的第一段和耦合到第二子集的第二段。 地址信号依次遍历该组存储器件。 存储器系统还包括耦合到存储器模块的存储器控​​制器。 存储器控制器包括第一电路，用于输出控制第一子集的第一控制信号，使得第一控制信号和地址信号在基本上同时到达第一子集中的存储器件。 存储器控制器还包括第二电路，用于输出控制第二子集的第二控制信号，使得第二控制信号和地址信号在基本上同时到达第二子集中的存储器件。

    Memory component with terminated and unterminated signaling inputs
    117.
    发明授权
    Memory component with terminated and unterminated signaling inputs 有权
    具有终止和未终止信号输入的存储器组件

    公开(公告)号：US08625371B2

    公开(公告)日：2014-01-07

    申请号：US13923634

    申请日：2013-06-21

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

    IPC: G11C7/00

    CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

    Abstract: A memory component has a signaling interface, data input/output (I/O) circuitry, command/address (CA) circuitry and clock generation circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component. The clock generation circuitry generates the first clock signal with a phase that establishes alignment between a leading edge of the bit time for each read data bit and a respective transition of the second clock signal.

    Abstract translation: 存储器组件具有信令接口，数据输入/输出（I / O）电路，命令/地址（CA）电路和时钟产生电路。 信令接口包括片上终端数据I / O和未终止的CA输入。 数据I / O电路专用于以由选通信号定时的数据I / O对写入数据位进行采样，并发送由第一时钟信号定时的读取数据位，每个写入和读取数据位对于位有效 时间在数据I / O。 CA电路在CA输入端采样CA信号，以第二时钟信号定时，CA信号指示要在存储器组件内执行的读和写操作。 时钟产生电路产生第一时钟信号，该相位在每个读取数据位的位时间的前沿和第二时钟信号的相应转换之间建立对齐。

    Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration
    118.
    发明申请
    Memory Component with Pattern Register Circuitry to Provide Data Patterns for Calibration 有权
    具有模式寄存器电路的存储器组件，用于提供用于校准的数据模式

    公开(公告)号：US20130346685A1

    公开(公告)日：2013-12-26

    申请号：US13967245

    申请日：2013-08-14

    Applicant: Rambus Inc.

    Inventor： Craig E. Hampel ,  Richard S. Perego ,  Stefanos Sidiropoulos ,  Ely K. Tsern ,  Frederick A. Ware

    IPC: G06F12/02

    CPC classification number: G11C11/4076 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0671 ,  G06F12/0246 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C7/222 ,  G11C11/40611 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/4093 ,  G11C21/00 ,  G11C2207/2254 ,  H04L7/0025 ,  H04L7/0079 ,  H04L7/0091

    Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

    Abstract translation: 存储器组件包括包含动态随机存取存储器（DRAM）存储单元的存储器核心和用于接收外部命令的第一电路。 外部命令包括指定发送从存储器核心访问的数据的读取命令。 存储器组件还包括响应于读取命令和在校准期间可操作以提供至少第一数据模式和第二数据模式的读取命令和模式寄存器电路将数据发送到外部总线的第二电路。 在校准期间，第一数据模式和第二数据模式中的所选择的一个被响应于在校准期间接收到的读命令，被第二电路发送到外部总线上。 此外，响应于在校准期间接收到的写入命令，第一和第二数据模式中的至少一个被写入模式寄存器电路。

    Memory Component with Terminated and Unterminated Signaling Inputs
    119.
    发明申请
    Memory Component with Terminated and Unterminated Signaling Inputs 有权
    具有终止和未终止信令输入的存储器组件

    公开(公告)号：US20130279278A1

    公开(公告)日：2013-10-24

    申请号：US13923634

    申请日：2013-06-21

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Ely K. Tsern ,  Richard E. Perego ,  Craig E. Hampel

    IPC: G11C7/22

    CPC classification number: G11C11/4076 ,  G06F1/06 ,  G06F1/105 ,  G06F1/12 ,  G06F3/0604 ,  G06F3/0658 ,  G06F3/0673 ,  G06F13/1684 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4086 ,  G11C5/063 ,  G11C7/04 ,  G11C7/1051 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/22 ,  G11C7/222 ,  G11C8/18 ,  G11C11/409 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50008 ,  G11C29/50012

    Abstract: A memory component has a signaling interface, data input/output (I/O) circuitry, command/address (CA) circuitry and clock generation circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input timed by a second clock signal, the CA signals indicating read and write operations to be performed within the memory component. The clock generation circuitry generates the first clock signal with a phase that establishes alignment between a leading edge of the bit time for each read data bit and a respective transition of the second clock signal.

    Abstract translation: 存储器组件具有信令接口，数据输入/输出（I / O）电路，命令/地址（CA）电路和时钟产生电路。 信令接口包括片上终端数据I / O和未终止的CA输入。 数据I / O电路专用于以由选通信号定时的数据I / O对写入数据位进行采样，并发送由第一时钟信号定时的读取数据位，每个写入和读取数据位对于位有效 时间在数据I / O。 CA电路在CA输入端采样CA信号，以第二时钟信号定时，CA信号指示要在存储器组件内执行的读和写操作。 时钟产生电路产生第一时钟信号，该相位在每个读取数据位的位时间的前沿和第二时钟信号的相应转换之间建立对齐。

    MEMORY MODULE WITH REDUCED READ/WRITE TURNAROUND OVERHEAD
    120.
    发明申请
    MEMORY MODULE WITH REDUCED READ/WRITE TURNAROUND OVERHEAD 有权

    公开(公告)号：US20250139026A1

    公开(公告)日：2025-05-01

    申请号：US18919066

    申请日：2024-10-17

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Craig E. Hampel

    IPC: G06F13/16 ,  G06F13/40 ,  G11C5/04 ,  G11C7/10 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096

    Abstract: A memory module includes a substrate, plural memory devices, and a buffer. The plural memory devices are organized into at least one rank, each memory device having plural banks. The buffer includes a primary interface for communicating with a memory controller and a secondary interface coupled to the plural memory devices. For each bank of each rank of memory devices, the buffer includes data buffer circuitry and address buffer circuitry. The data buffer circuitry includes first storage to store write data transferred during a bank cycle interval (tRR). The address buffer circuitry includes second storage to store address information corresponding to the data stored in the first storage.

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