公开(公告)号：US08935594B2

公开(公告)日：2015-01-13

申请号：US13052762

申请日：2011-03-21

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  I-Jen Huang

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  I-Jen Huang

IPC: G11C29/00 ,  H01L27/06 ,  G06F11/10 ,  H01L27/115

CPC classification number: H01L27/0688 ,  G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1072 ,  G06F11/1076 ,  H01L27/11573 ,  H01L27/11578

Abstract: A structure of 3D memory comprises a plurality of stacking layers and a plurality of cells. The stacking layers are arranged in a three-dimensional array and disposed parallel to each other on a substrate, and the stacking layers comprises a plurality of stacking memory layers. The cells comprises a first group of cells (such as m of cells) for storing information data and a second group of cells (such as n of cells) for storing ECC (error checking and correcting) spare bits. All of the first group and the second group of cells are read out at the same time for performing an ECC function. The ECC spare bits in the 3D memory according to the present disclosure can be constructed at the same physical layer or at the different physical layers. The embodiments can be implemented, but not limited, by a vertical-gate (VG) structure or a finger VG structure.

Abstract translation: 3D存储器的结构包括多个堆叠层和多个单元。 堆叠层被布置成三维阵列并且在衬底上彼此平行地布置，并且层叠层包括多个层叠存储层。 这些单元包括用于存储信息数据的第一组单元（例如，单元格m）和用于存储ECC（错误检查和校正）备用位的第二组单元（例如n个单元）。 同时读出所有第一组和第二组单元，以执行ECC功能。 根据本公开的3D存储器中的ECC备用位可以在相同的物理层或不同的物理层构造。 实施例可以通过垂直门（VG）结构或手指VG结构来实现但不限于此。

公开(公告)号：US08916845B2

公开(公告)日：2014-12-23

申请号：US13324946

申请日：2011-12-13

Applicant: Shih-Hung Chen ,  Yi-Chou Chen

Inventor： Shih-Hung Chen ,  Yi-Chou Chen

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/122 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1641 ,  H01L45/1675 ,  Y10S977/943

Abstract: Memory cells described herein have an increased current density at lateral edges of the active region compared to that of conventional mushroom-type memory cells, resulting in improved operational current efficiency. As a result, the amount of heat generated within the lateral edges per unit value of current is increased relative to that of conventional mushroom-type memory cells. Therefore, the amount of current needed to induce phase change is reduced.

Abstract translation: 与传统的蘑菇型存储器单元相比，本文所述的存储单元在有源区域的横向边缘处具有增加的电流密度，从而提高了操作电流效率。 结果，相对于传统的蘑菇型存储单元，每单位电流值在横向边缘内产生的热量增加。 因此，引起相变所需的电流量减少。

公开(公告)号：US08907316B2

公开(公告)日：2014-12-09

申请号：US12267453

申请日：2008-11-07

Applicant: Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

Inventor： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

IPC: H01L47/00 ,  H01L45/00 ,  H01L27/102 ,  H01L27/24 ,  H01L29/861 ,  H01L29/165 ,  H01L29/04 ,  G11C13/00

CPC classification number: H01L29/8616 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/04 ,  H01L29/165 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

Abstract: A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn-junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn-junction between the first and second regions.

Abstract translation: 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体区域，第一和 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区形成在单晶半导体中，并且所述第二掺杂半导体区包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与所述第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定所述第一和第二区域之间的pn结。

公开(公告)号：US20140078804A1

公开(公告)日：2014-03-20

申请号：US13619124

申请日：2012-09-14

Applicant: Chih-Chang Hsieh ,  Shih-Hung Chen ,  Hang-Ting Lue

Inventor： Chih-Chang Hsieh ,  Shih-Hung Chen ,  Hang-Ting Lue

IPC: G11C5/06 ,  G03F1/38 ,  G06F17/50

CPC classification number: G03F1/36 ,  G03F1/38 ,  G11C5/025 ,  G11C5/063

Abstract: A lithography mask and method for manufacturing such mask that includes optically isolated via features and proximity correction features. The via patterns that include via features that define vias are positioned on the mask in rows and columns with a row and a column pitch between each row and column on the mask. The via patterns are positioned such that via features that are in adjacent columns are separated by at least one intervening row between them. The via patterns can also be positioned such that the via patterns that are in adjacent rows are separated by at least one intervening column between them. As a result, the via feature of each via pattern and the associated optical proximity correction features that are positioned around each via feature do not overlap with the optical proximity correction features and the via features of the surrounding via patterns.

Abstract translation: 一种光刻掩模和用于制造这种掩模的方法，其包括光学隔离的特征和接近校正特征。 包括定义通孔的通孔特征的通孔图案以掩模上每行和列之间的行和列间距的行和列定位在掩模上。 通孔图案被定位成使得相邻列中的通孔特征由它们之间的至少一个中间行分开。 通孔图案也可以被定位成使得相邻行中的通孔图案被它们之间的至少一个中间柱隔开。 结果，每个通孔图案的通孔特征和位于每个通孔特征周围的相关联的光学邻近校正特征不与周围通孔图案的光学邻近校正特征和通孔特征重叠。

公开(公告)号：US08664689B2

公开(公告)日：2014-03-04

申请号：US12267492

申请日：2008-11-07

Applicant: Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

Inventor： Hsiang-Lan Lung ,  Erh-Kun Lai ,  Yen-Hao Shih ,  Yi-Chou Chen ,  Shih-Hung Chen

IPC: H01L29/861 ,  H01L29/88

CPC classification number: H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2463 ,  H01L27/2472 ,  H01L29/861 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675 ,  H01L45/1683

Abstract: A memory device includes a driver comprising a pn-junction in the form of a multilayer stack including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor plug having a second conductivity type opposite the first conductivity type, the first and second doped semiconductors defining a pn junction therebetween, in which the first doped semiconductor region is formed in a single-crystalline semiconductor, and the second doped semiconductor region includes a polycrystalline semiconductor. Also, a method for making a memory device includes forming a first doped semiconductor region of a first conductivity type in a single-crystal semiconductor, such as on a semiconductor wafer; and forming a second doped polycrystalline semiconductor region of a second conductivity type opposite the first conductivity type, defining a pn junction between the first and second regions.

Abstract translation: 存储器件包括驱动器，其包括多层堆叠形式的pn结，其包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体插头，第一和第 第二掺杂半导体，其中限定其间的pn结，其中所述第一掺杂半导体区域形成在单晶半导体中，并且所述第二掺杂半导体区域包括多晶半导体。 此外，制造存储器件的方法包括在半导体晶片上形成单晶半导体中的第一导电类型的第一掺杂半导体区域; 以及形成与第一导电类型相反的第二导电类型的第二掺杂多晶半导体区域，限定第一和第二区域之间的pn结。

公开(公告)号：US20140054784A1

公开(公告)日：2014-02-27

申请号：US13594372

申请日：2012-08-24

Applicant: Shih-Hung Chen

Inventor： Shih-Hung Chen

IPC: H01L21/768 ,  H01L23/535

CPC classification number: H01L23/522 ,  H01L21/76816 ,  H01L21/76888 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A connector access region of an integrated circuit device includes a set of parallel conductors, extending in a first direction, and interlayer connectors. The conductors comprise a set of electrically conductive contact areas on different conductors which define a contact plane with the conductors extending below the contact plane. A set of the contact areas define a line at an oblique angle, such as less than 45° or 5° to 27°, to the first direction. The interlayer connectors are in electrical contact with the contact areas and extend above the contact plane. At least some of the interlayer connectors overlie but are electrically isolated from the electrical conductors adjacent to the contact areas with which the interlayer connectors are in electrical contact. The set of parallel conductors may include a set of electrically conductive layers with the contact plane being generally perpendicular to the electrically conductive layers.

Abstract translation: 集成电路器件的连接器接入区域包括沿第一方向延伸的一组平行导体和层间连接器。 导体包括在不同导体上的一组导电接触区域，其限定了在接触平面下方延伸的导体的接触平面。 一组接触区域以相对于第一方向的倾斜角度（例如小于45°或5°至27°）限定一条线。 层间连接器与接触区域电接触并在接触面上方延伸。 层间连接器中的至少一些覆盖在电绝缘体上，并与电接触部分相邻的电导体隔离。 该组平行导体可以包括一组导电层，其中接触平面大致垂直于导电层。

公开(公告)号：US20140054535A1

公开(公告)日：2014-02-27

申请号：US13594353

申请日：2012-08-24

Applicant: Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

Inventor： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang-Yeu Hsieh ,  Erh-Kun Lai ,  Yen-Hao Shih

IPC: H01L47/00

CPC classification number: H01L27/11582 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575

Abstract: A semiconductor structure with improved capacitance of bit lines includes a substrate, a stacked memory structure, a plurality of bit lines, a first stair contact structure, a first group of transistor structures and a first conductive line. The first stair contact structure is formed on the substrate and includes conductive planes and insulating planes stacked alternately. The conductive planes are separated from each other by the insulating planes for connecting the bit lines to the stacked memory structure by stairs. The first group of transistor structures is formed in a first bulk area where the bit lines pass through and then connect to the conductive planes. The first group of transistor structures has a first gate around the first bulk area. The first conductive line is connected to the first gate to control the voltage applied to the first gate.

Abstract translation: 具有改善的位线电容的半导体结构包括衬底，堆叠存储器结构，多个位线，第一阶梯接触结构，第一组晶体管结构和第一导电线。 第一阶梯接触结构形成在基板上，并且包括交替堆叠的导电平面和绝缘面。 导电平面通过用于通过楼梯将位线连接到堆叠的存储器结构的绝缘平面彼此分离。 第一组晶体管结构形成在第一体积区域中，其中位线通过，然后连接到导电平面。 第一组晶体管结构在第一体积区域周围具有第一栅极。 第一导线连接到第一栅极以控制施加到第一栅极的电压。

公开(公告)号：US20130277799A1

公开(公告)日：2013-10-24

申请号：US13451428

申请日：2012-04-19

Applicant: Shih-Hung Chen ,  Kuang-Yeu Hsieh

Inventor： Shih-Hung Chen ,  Kuang-Yeu Hsieh

IPC: H01L29/92 ,  H01L21/02

CPC classification number: H01L28/91

Abstract: An example of a capacitor includes a series of ridges and trenches and an interconnect region on the integrated circuit substrate. The series of ridges and trenches and the interconnect region have a capacitor foundation surface with a serpentine cross-sectional shape on the series of ridges and trenches. Electrical conductors are electrically connected to the electrode layers from the interconnect region for access to the electrode layers of the capacitor assembly.

Abstract translation: 电容器的示例包括集成电路基板上的一系列脊和沟槽和互连区域。 一系列脊和沟槽和互连区域具有在一系列脊和沟槽上具有蛇形横截面形状的电容器基座表面。 电导体从互连区域电连接到电极层，用于进入电容器组件的电极层。

公开(公告)号：US08541882B2

公开(公告)日：2013-09-24

申请号：US13240058

申请日：2011-09-22

Applicant: Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

Inventor： Shih-Hung Chen ,  Yan-Ru Chen ,  Lo-Yueh Lin

IPC: H01L23/48 ,  H01L21/283

CPC classification number: G11C5/04 ,  G11C5/06 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L27/0688 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: An IC device comprises a stack of contact levels, each including conductive layer and an insulation layer. A dielectric liner surrounds an interlevel conductor within an opening in the stack of contact levels. The opening passes through a portion of the stack of contact levels. The interlevel conductor is electrically insulated from the conductive layers of each of the contact levels through the dielectric liner. A portion of the conductive layer at the opening is recessed relative to adjacent insulation layers. The dielectric liner may have portions extending between adjacent insulation layers.

Abstract translation: IC器件包括一叠接触电平，每一层包括导电层和绝缘层。 电介质衬垫围绕接触层叠层内的开口内的层间导体。 开口穿过一叠接触层的一部分。 层间导体与通过电介质衬垫的每个接触层的导电层电绝缘。 开口处的导电层的一部分相对于相邻的绝缘层凹入。 电介质衬垫可以具有在相邻绝缘层之间延伸的部分。

公开(公告)号：US20130153846A1

公开(公告)日：2013-06-20

申请号：US13330525

申请日：2011-12-19

Applicant: Wei-Chih CHIEN ,  Ming-Hsiu Lee ,  Shih-Hung Chen

Inventor： Wei-Chih CHIEN ,  Ming-Hsiu Lee ,  Shih-Hung Chen

IPC: H01L45/00 ,  H01L21/8239

CPC classification number: H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1633

Abstract: A self-aligning stacked memory cell array structure and method for fabricating such structure. The memory cell array includes a stack of memory cells disposed adjacent to opposing sides of a conductive line that is formed within a trench. The memory cells are stacked such that the memory element surface of each memory cell forms a portion of the sidewall of the conductive line. The conductive line is formed within the trench such that electrical contact is made across the entire memory element surface of each memory cell. Such structure and method for making such structure is a self-aligning process that does not require the use of any additional masks.

Abstract translation: 一种自对准堆叠式存储单元阵列结构及其制造方法。 存储单元阵列包括与形成在沟槽内的导电线的相对侧相邻设置的一堆存储单元。 存储单元被堆叠，使得每个存储单元的存储元件表面形成导电线的侧壁的一部分。 导电线形成在沟槽内，使得电接触跨越每个存储单元的整个存储元件表面。 用于制造这种结构的这种结构和方法是不需要使用任何附加掩模的自对准过程。