公开(公告)号：US20240023327A1

公开(公告)日：2024-01-18

申请号：US18357278

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin

IPC: H10B20/20 ,  G11C17/18 ,  G11C17/16

CPC classification number: H10B20/20 ,  G11C17/18 ,  G11C17/16

Abstract: In some embodiments, the present disclosure relates to an integrated chip (IC) memory structure. The IC memory structure includes a first conductor over a substrate and a second conductor over the first conductor. The first conductor is vertically separated from the second conductor by an isolation structure. A first channel structure is arranged on a sidewall of the isolation structure. The first channel structure is vertically between the first conductor and the second conductor. A vertical gate electrode is disposed along sidewalls of the first conductor, the second conductor, and the first channel structure. The sidewall of the first channel structure faces away from the isolation structure.

公开(公告)号：US11849644B2

公开(公告)日：2023-12-19

申请号：US17231320

申请日：2021-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chang-Lin Yang ,  Chung-Te Lin ,  Sheng-Yuan Chang ,  Han-Ting Lin ,  Chien-Hua Huang

IPC: H10N50/01 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/01 ,  H10B61/00 ,  H10N50/80

Abstract: A method for fabricating magnetoresistive random-access memory cells (MRAM) on a substrate is provided. The substrate is formed with a magnetic tunneling junction (MTJ) layer thereon. When the MTJ layer is etched to form the MRAM cells, there may be metal components deposited on a surface of the MRAM cells and between the MRAM cells. The metal components are then removed by chemical reaction. However, the removal of the metal components may form extra substances on the substrate. A further etching process is then performed to remove the extra substances by physical etching.

公开(公告)号：US20230389320A1

公开(公告)日：2023-11-30

申请号：US18446582

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Feng-Ching Chu ,  Feng-Cheng Yang ,  Katherine H. Chiang ,  Chung-Te Lin ,  Chieh-Fang Chen

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: The present disclosure provides a semiconductor structure and a method for forming a semiconductor structure. The semiconductor structure includes a substrate, and a dielectric stack over the substrate. The dielectric stack includes a first layer over the substrate and a second layer over the first layer. The semiconductor structure further includes a gate layer including a first portion traversing the second layer and a second portion extending between the first layer and the second layer.

公开(公告)号：US20230369420A1

公开(公告)日：2023-11-16

申请号：US18357264

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yen-Chieh Huang ,  Po-Ting Lin ,  Song-Fu Liao ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H01L21/28 ,  H01L29/78 ,  H01L29/66 ,  H10B51/00

CPC classification number: H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/00

Abstract: In some embodiments, the present disclosure relates to an integrated circuit (IC). The IC includes a substrate and an electrode disposed over the substrate. A ferroelectric layer is vertically stacked with the electrode. A seed layer that includes oxygen is vertically stacked between the electrode and the ferroelectric layer. The ferroelectric layer has a substantially uniform orthorhombic crystalline phase.

公开(公告)号：US20230369107A1

公开(公告)日：2023-11-16

申请号：US18357251

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Li-Shyue Lai ,  Gao-Ming Wu ,  Katherine H. Chiang ,  Chung-Te Lin

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76831 ,  H01L23/5226 ,  H01L21/76877 ,  H01L21/76832

Abstract: An integrated circuit device includes a dielectric structure within a metal interconnect over a substrate. The dielectric structure includes a cavity. A first dielectric layer provides a roof for the cavity. A second dielectric layer provides a floor for the cavity. A material distinct from the first dielectric layer and the second dielectric layer provides a side edge for the cavity. In a central area of the cavity, the cavity has a constant height. The height may be selected to provide a low parasitic capacitance between features above and below the cavity. The roof of the cavity may be flat. A gate dielectric may be formed over the roof. The dielectric structure is particularly useful for reducing parasitic capacitances when employing back-end-of-line (BEOL) transistors.

公开(公告)号：US11818894B2

公开(公告)日：2023-11-14

申请号：US17460294

申请日：2021-08-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chia-Yu Ling ,  Katherine H. Chiang ,  Chung-Te Lin

IPC: H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/10

Abstract: Provided is a memory cell including a channel material contacting a source line and a bit line; a ferroelectric (FE) material contacting the channel material; and a word line contacting the FE material. The FE material is disposed between the channel material and the word line. The word line includes a bulk layer. The bulk layer includes a first metal layer; and a second metal layer. The second metal layer is sandwiched between the first metal layer and the FE material.

公开(公告)号：US20230363181A1

公开(公告)日：2023-11-09

申请号：US18356585

申请日：2023-07-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Sheng-Chih Lai ,  Chung-Te Lin ,  Min Cao ,  Randy Osborne

IPC: H10B61/00 ,  G11C11/16 ,  H10N50/10 ,  H10N50/80

CPC classification number: H10B61/10 ,  G11C11/1673 ,  G11C11/161 ,  G11C11/1675 ,  G11C11/1659 ,  H10N50/10 ,  H10N50/80

Abstract: Various embodiments of the present application are directed towards a bipolar selector having independently tunable threshold voltages, as well as a memory cell comprising the bipolar selector and a memory array comprising the memory cell. In some embodiments, the bipolar selector comprises a first unipolar selector and a second unipolar selector. The first and second unipolar selectors are electrically coupled in parallel with opposite orientations and may, for example, be diodes or some other suitable unipolar selectors. By placing the first and second unipolar selectors in parallel with opposite orientations, the first unipolar selector independently defines a first threshold voltage of the bipolar selector and the second unipolar selector independently defines a second threshold voltage of the bipolar selector. As a result, the first and second threshold voltages can be independently tuned by adjusting parameters of the first and second unipolar selectors.

公开(公告)号：US20230329000A1

公开(公告)日：2023-10-12

申请号：US18335167

申请日：2023-06-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Rainer Yen-Chieh Huang ,  Hai-Ching Chen ,  Chung-Te Lin

IPC: H10B51/30 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L29/786

CPC classification number: H10B51/30 ,  H01L23/5226 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/516 ,  H01L29/78687 ,  H01L29/7869 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78648 ,  H01L29/66765 ,  H01L29/78693 ,  H10B51/00

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a gate electrode over a substrate, and a gate dielectric layer arranged over the gate electrode. The gate dielectric layer includes a ferroelectric material. An active structure is arranged over the gate dielectric layer and includes a semiconductor material. A source contact and a drain contact are arranged over the active structure. A capping structure is arranged between the source and drain contacts and over the active structure. The capping structure includes a first metal material.

公开(公告)号：US11784219B2

公开(公告)日：2023-10-10

申请号：US17339171

申请日：2021-06-04

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Mark Van Dal ,  Gerben Doornbos ,  Chung-Te Lin

IPC: H01L21/82 ,  H01L27/092 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L27/06 ,  H01L21/8238 ,  H01L21/822 ,  H01L29/40 ,  H01L29/08 ,  H01L29/786 ,  B82Y10/00 ,  H01L29/775 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02236 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0688 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/6681 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: Methods for forming semiconductor structures are provided. The method includes forming a fin structure over a substrate and forming a dummy gate structure across the fin structure. The method further includes forming a spacer layer on a sidewall of the fin structure at a source/drain region. The method further includes removing at least a portion of the spacer layer to enlarge the source/drain region and forming a source/drain structure in the source/drain region.

公开(公告)号：US11744080B2

公开(公告)日：2023-08-29

申请号：US17121757

申请日：2020-12-15

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Yi-Ching Liu ,  Chia-En Huang ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C7/18 ,  G11C8/14 ,  H01L23/522 ,  H10B51/10 ,  H10B51/30

CPC classification number: H10B51/20 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5226 ,  H10B51/10 ,  H10B51/30

Abstract: A memory device, a semiconductor device and manufacturing methods for forming the memory device and the semiconductor device are provided. The memory device include a stacking structure, a switching layer, channel layers and pairs of conductive pillars. The stacking structure includes alternately stacked isolation layers and word lines, and extends along a first direction. The stacking structure has a staircase portion and a connection portion at an edge region of the stacking structure. The connection portion extends along the staircase portion and located aside the staircase portion, and may not be shaped into a staircase structure. The switching layer covers a sidewall of the stacking structure. The channel layers cover a sidewall of the switching layer, and are laterally spaced apart from one another along the first direction. The pairs of conductive pillars stand on the substrate, and in lateral contact with the switching layer through the channel layers.