公开(公告)号：US5110754A

公开(公告)日：1992-05-05

申请号：US771688

申请日：1991-10-04

申请人： Tyler A. Lowrey ,  Kevin G. Duesman ,  Eugene H. Cloud

发明人： Tyler A. Lowrey ,  Kevin G. Duesman ,  Eugene H. Cloud

IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/118

CPC分类号： H01L27/10852 ,  H01L21/76888 ,  H01L23/5252 ,  H01L27/118 ,  H01L2924/0002

摘要： The invention is directed to a concept to use a 3-dimensional DRAM capacitor as a one-time non-volatile programming element (programmable antifuse) to make redundancy repair and/or to select other options on a DRAM. The programmable element of the present invention provides some significant advantages, such as a lower programming voltage, which allows use of the DRAM's existing operating supply, and requiring only half of the operating voltage to test the element once programming is accomplished. The lower programming voltage allows for redundancy repair of defective DRAM cells (or selecting other options) to be made after the DRAM die is packaged including after it is installed at a customer's site.

摘要翻译： 本发明涉及使用三维DRAM电容器作为一次性非易失性编程元件（可编程反熔丝）来进行冗余修复和/或在DRAM上选择其它选项的概念。 本发明的可编程元件提供了一些显着的优点，例如较低的编程电压，其允许使用DRAM的现有操作电源，并且一旦完成编程，则仅需要一半的工作电压来测试元件。 较低的编程电压允许在DRAM裸片封装之后进行的故障DRAM单元的冗余修复（或选择其他选项），包括在安装在客户现场之后。

公开(公告)号：US5069747A

公开(公告)日：1991-12-03

申请号：US633573

申请日：1990-12-21

申请人： David A. Cathey ,  Mark E. Tuttle ,  Ruojia Lee ,  Tyler A. Lowrey

发明人： David A. Cathey ,  Mark E. Tuttle ,  Ruojia Lee ,  Tyler A. Lowrey

IPC分类号： H01L21/033 ,  H01L21/266 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/31612 ,  H01L29/6656

摘要： A process for creating and removing temporary silicon dioxide structures on an in-process integrated circuit with minimal effect on existing permanent silicon dioxide structures that are exposed. The process comprises the steps of blanket depositing an ozone-TEOS silicon dioxide layer through chemical vapor deposition on top of the in-process integrated circuit, thus covering permanent structures formed from conventional silicon dioxides (e.g. TEOS and thermal oxides), etching the ozone-TEOS layer to create said temporary structures, and removing the temporary structures using dilute hydrofluoric acid.

摘要翻译： 一种用于在过程中集成电路中创建和去除临时二氧化硅结构的方法，对暴露的现有永久性二氧化硅结构的影响最小。 该方法包括以下步骤：通过化学气相沉积在过程中集成电路的顶部覆盖沉积臭氧-TEOS二氧化硅层，从而覆盖由常规二氧化硅（例如TEOS和热氧化物）形成的永久结构， TEOS层以产生所述临时结构，并使用稀氢氟酸除去临时结构。

公开(公告)号：US5057449A

公开(公告)日：1991-10-15

申请号：US498669

申请日：1990-03-26

申请人： Tyler A. Lowrey ,  Fernando Gonzalez ,  Joseph J. Karniewicz

发明人： Tyler A. Lowrey ,  Fernando Gonzalez ,  Joseph J. Karniewicz

IPC分类号： H01L21/28 ,  H01L21/316 ,  H01L21/32 ,  H01L21/8234 ,  H01L21/8242

CPC分类号： H01L27/10873 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/28167 ,  H01L21/31662 ,  H01L21/32 ,  H01L21/823462 ,  H01L21/28211 ,  Y10S148/163

摘要： A process for creating two thicknesses or gate oxide within a dynamic random memory. The process begins by thermally growing a first layer of gate oxide on a silicon substrate. This first layer is then masked with photoresist in regions where cell access transistors will ultimately be fabricated. All oxide that is not masked is then removed with an oxide etch. After the photoresist is stripped, a second layer of gate oxide is thermally grown on the substrate. The resultant oxided layer, which comprises multiple-thickness components, is used as a pad oxide layer during a conventional LOCOS operation. Peripheral driver transistors are construction on top of a thin layer of gate oxide so as to optimize their performance, whereas, cell access transistors are constructed on top of a thicker layer of gate oxide so as to minimize row line capacitance. A net increase in row line access speed is thus obtained.

摘要翻译： 在动态随机存储器内创建两个厚度或栅极氧化物的工艺。 该过程开始于在硅衬底上热生长第一层栅极氧化物。 然后在最终将制造单元存取晶体管的区域中用光致抗蚀剂掩蔽该第一层。 然后用氧化物蚀刻去除未被掩蔽的全部氧化物。 在剥离光致抗蚀剂之后，在衬底上热生长第二层栅氧化层。 在常规LOCOS操作期间，将包含多个厚度成分的所得氧化层用作衬垫氧化物层。 外围驱动器晶体管是在栅极氧化物的薄层之上构建的，以便优化其性能，而单元存取晶体管构造在较厚的栅极氧化物层之上，以便使行线电容最小化。 从而获得行线访问速度的净增加。

公开(公告)号：US5032545A

公开(公告)日：1991-07-16

申请号：US605748

申请日：1990-10-30

申请人： Trung T. Doan ,  Tyler A. Lowrey

发明人： Trung T. Doan ,  Tyler A. Lowrey

IPC分类号： H01L21/306 ,  H01L21/318 ,  H01L21/334

CPC分类号： H01L21/02046 ,  H01L21/3185 ,  H01L29/66181 ,  Y10S438/906 ,  Y10S438/974

摘要： A process for forming silicon nitride layers on silicon substrates which includes initially heating the silicon substrates in a rapid thermal processor and in a substantially oxygen-free and residual moisture free environment to form a thin Si.sub.3 N.sub.4 layer directly on the silicon surface which is free of any measurable native SiO.sub.2 thereon. Then, the nitridized wafers are transferred into a conventional nitride furnace where the thin Si.sub.3 N.sub.4 layers may be increased in thickness by a desired amount. Typically, the initial or first Si.sub.3 N.sub.4 layer thickness will be about 10-30 angstroms and the second Si.sub.3 N.sub.4 layer will be on the order of 80 angstroms or more to form a composite Si.sub.3 N.sub.4 layer of about 100-150 angstroms in total thickness. This novel process and the high dielectric constant integrated circuit capacitors produced thereby are highly useful in the manufacture of certain very large scale integrated circuit (VLSI) components such as dynamic random access memories and the like.

摘要翻译： 一种用于在硅衬底上形成氮化硅层的工艺，其包括在快速热处理器中和基本上无氧且无残留的无水环境中初始加热硅衬底，以直接在硅表面上形成薄的Si 3 N 4层， 可测量的天然SiO2。 然后，将氮化的晶片转移到常规的氮化物炉中，其中薄的Si 3 N 4层可以以期望的量增加。 通常，初始或第一Si 3 N 4层的厚度为约10-30埃，而第二Si 3 N 4层将为约80埃或更多，以形成约100-150埃的总厚度的复合Si 3 N 4层。 由此产生的这种新颖的工艺和高介电常数集成电路电容器在制造诸如动态随机存取存储器等的某些大规模集成电路（VLSI）组件中是非常有用的。

公开(公告)号：US5026657A

公开(公告)日：1991-06-25

申请号：US491784

申请日：1990-03-12

申请人： Ruojia Lee ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  Joseph J. Karniewicz ,  Pierre C. Fazan

发明人： Ruojia Lee ,  Tyler A. Lowrey ,  Fernando Gonzalez ,  Joseph J. Karniewicz ,  Pierre C. Fazan

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8242

CPC分类号： H01L27/10844 ,  H01L21/823835 ,  H01L29/665 ,  Y10S257/90

摘要： A split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates and N+ regions with a minimum of additional processing steps. By employing a light oxidation step to protect the P-channel transistor sidewall gates from silicidation during a subsequent processing step, the process avoids the problems that may be created by the double etching of the field oxide and active area regions that has heretofore been required for self-aligned silidation utilizing a split-polysilicon CMOS process. A protective nitride layer is used to prevent oxidation on those regions which are to be silicided. When this improved process is utilized for DRAM fabrication, the protective nitride layer may also be utilized as the cell dielectric. Although this process precludes the silicidation of the sources and drains of P-channel transistors, silicidation of other important regions is accomplished with very few steps required beyond those required for the basic split-polysilicon CMOS process without self-aligned silicidation of conductive regions.

摘要翻译： 分离多晶硅CMOS DRAM工艺，其结合了单元板，晶体管栅极和N +区域的自对准硅化，具有最小的附加处理步骤。 通过采用光氧化步骤来在随后的处理步骤期间保护P沟道晶体管侧壁栅极不被硅化，该过程避免了可能由现场氧化物和有源区域的双重蚀刻产生的问题， 利用分裂多晶硅CMOS工艺进行自对准硅化。 使用保护性氮化物层来防止要被硅化的那些区域上的氧化。 当这种改进的工艺用于DRAM制造时，保护性氮化物层也可以用作电池电介质。 尽管这个过程排除了P沟道晶体管的源极和漏极的硅化，但是除了不需要导电区域的自对准硅化的基本分裂多晶硅CMOS工艺所需要的步骤之外，其它重要区域的硅化是非常少的步骤。

公开(公告)号：US08034716B2

公开(公告)日：2011-10-11

申请号：US12434212

申请日：2009-05-01

申请人： Fernando Gonzalez ,  Tyler A. Lowrey ,  Trung T. Doan ,  Raymond A. Turi ,  Graham R. Wolstenholme

发明人： Fernando Gonzalez ,  Tyler A. Lowrey ,  Trung T. Doan ,  Raymond A. Turi ,  Graham R. Wolstenholme

IPC分类号： H01L21/44

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/0814 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/861 ,  H01L45/04 ,  H01L45/145 ,  Y10S257/903 ,  Y10S257/91 ,  Y10S438/979

摘要： Semiconductor structures and methods of making a vertical diode structure are provided. The vertical diode structure may have associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer may be formed over the interior surface of the diode opening and contacting the active region. The diode opening may initially be filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that may be heavily doped with a first type dopant and a bottom portion that may be lightly doped with a second type dopant. The top portion may be bounded by the bottom portion so as not to contact the titanium silicide layer. In one embodiment of the vertical diode structure, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

摘要翻译： 提供了制造垂直二极管结构的半导体结构和方法。 垂直二极管结构可以具有延伸穿过绝缘层并接触硅晶片上的有源区的二极管开口。 硅化钛层可以形成在二极管开口的内表面上并与活性区接触。 二极管开口最初可以填充非晶硅插塞，其在沉积期间被掺杂并随后重结晶以形成大晶粒多晶硅。 硅插头具有可以重掺杂第一类型掺杂剂的顶部部分和可以轻掺杂第二类型掺杂剂的底部部分。 顶部可以由底部限定，以便不与硅化钛层接触。 在垂直二极管结构的一个实施例中，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

公开(公告)号：US07671356B2

公开(公告)日：2010-03-02

申请号：US11265275

申请日：2005-11-03

申请人： Isamu Asano ,  Tyler A. Lowrey

发明人： Isamu Asano ,  Tyler A. Lowrey

IPC分类号： H01L47/00

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  G11C2213/52 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

摘要： A non-volatile memory element comprising a bottom electrode 12, a top electrode 17 provided on the bottom electrode 12, and a recording layer 18 containing phase change material connected between the bottom electrode 12 and the top electrode 17. In accordance with this invention, the top electrode 17 is in contact with a growth initiation surface 18a of the recording layer 17. This structure can be obtained by forming the top electrode 17 before the recording layer 18, resulting in a three-dimensional structure. This decreases heat dissipation to the bit line without increasing the thickness of the recording layer 18.

摘要翻译： 包括底部电极12，设置在底部电极12上的顶部电极17和包含连接在底部电极12和顶部电极17之间的相变材料的记录层18的非易失性存储元件。根据本发明， 顶部电极17与记录层17的生长起始表面18a接触。这种结构可以通过在记录层18之前形成顶部电极17而获得，从而形成三维结构。 这降低了对位线的散热，而不增加记录层18的厚度。

公开(公告)号：US07589343B2

公开(公告)日：2009-09-15

申请号：US10319764

申请日：2002-12-13

申请人： Tyler A. Lowrey

发明人： Tyler A. Lowrey

IPC分类号： H01L47/00

CPC分类号： H01L27/2427 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1675

摘要： Briefly, in accordance with an embodiment of the invention, a memory and a method to manufacture the memory is provided. The memory may include a phase change material over a substrate. The memory may further include a switching material coupled to the phase change material, wherein the switching material comprises a chalcogen other than oxygen and wherein the switching material and the phase change material form portions of a vertical structure over the substrate.

摘要翻译： 简而言之，根据本发明的实施例，提供了一种用于制造存储器的存储器和方法。 存储器可以包括在衬底上的相变材料。 存储器还可以包括耦合到相变材料的开关材料，其中开关材料包括除氧以外的硫族元素，并且其中开关材料和相变材料在衬底上形成垂直结构的部分。

公开(公告)号：US07414883B2

公开(公告)日：2008-08-19

申请号：US11407573

申请日：2006-04-20

申请人： George A. Gordon ,  Ward D. Parkinson ,  John M. Peters ,  Tyler A. Lowrey ,  Stanford Ovshinsky ,  Guy C. Wicker ,  Ilya V. Karpov ,  Charles C. Kuo

发明人： George A. Gordon ,  Ward D. Parkinson ,  John M. Peters ,  Tyler A. Lowrey ,  Stanford Ovshinsky ,  Guy C. Wicker ,  Ilya V. Karpov ,  Charles C. Kuo

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/77 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

摘要： A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.

摘要翻译： 可以用稳定的硫属化物玻璃来实现记忆，硫化物玻璃被定义为当暴露于200℃下30分钟或更短时不改变为通常结晶相的通常为非晶态的硫族化物材料。 可以通过改变材料的阈值电压来编程不同的状态。 可以用不同幅度和/或不同脉冲下降时间的脉冲来改变阈值电压。 可以使用两种不同状态的阈值电压之间的参考电平进行读取。 通常不需要单独的访问设备。

公开(公告)号：US07308067B2

公开(公告)日：2007-12-11

申请号：US10633872

申请日：2003-08-04

申请人： Tyler A. Lowrey ,  Ward D. Parkinson

发明人： Tyler A. Lowrey ,  Ward D. Parkinson

IPC分类号： G11C16/04

CPC分类号： G11C13/004 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/76

摘要： A read bias scheme may be used for phase change memories including a chalcogenide access device and a chalcogenide memory element. Through an appropriate read bias scheme, desirable read margin can be achieved. This may result in better yield, higher reliability, and ultimately lower costs in some cases.

摘要翻译： 读偏置方案可用于包括硫族化物存取装置和硫族化物存储元件的相变存储器。 通过适当的读取偏置方案，可以实现理想的读取余量。 这可能导致更好的产量，更高的可靠性，并且在某些情况下最终降低成本。