公开(公告)号：US5909399A

公开(公告)日：1999-06-01

申请号：US100330

申请日：1998-06-19

申请人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

发明人： Tomoharu Tanaka ,  Masaki Momodomi ,  Hideo Kato ,  Hiroto Nakai ,  Yoshiyuki Tanaka ,  Riichiro Shirota ,  Seiichi Aritome ,  Yasuo Itoh ,  Yoshihisa Iwata ,  Hiroshi Nakamura ,  Hideko Odaira ,  Yutaka Okamoto ,  Masamichi Asano ,  Kaoru Tokushige

IPC分类号： G06F11/10 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/52 ,  G11C13/00

CPC分类号： G11C29/785 ,  G06F11/1008 ,  G11C16/10 ,  G11C16/12 ,  G11C16/24 ,  G11C16/3436 ,  G11C16/344 ,  G11C16/3454 ,  G11C29/34 ,  G11C29/52 ,  G06F11/1068 ,  G06F2201/81 ,  G06F2212/2022

摘要： The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

摘要翻译： 可以缩短程序验证和擦除验证操作所需的时间。 即使重复执行写入和擦除操作，也可以抑制存储单元的阈值变化。 在编程和擦除操作之后，可以根据每个位线上的电位的预充电之后的所有位线同时判断操作，而不改变列地址。 在数据重写过程中，通过改变数据寄存器中的数据，对数据一次正确写入的存储单元不会影响重写操作。

公开(公告)号：US5831903A

公开(公告)日：1998-11-03

申请号：US868138

申请日：1997-06-03

申请人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

发明人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/00 ,  G11C29/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454

摘要： A NAND cell type electrically erasable programmable read-only memory has a memory array section containing NAND cell units. Each NAND cell unit has a series array of floating gate type metal-oxide semiconductor field effect transistors as memory cell transistors. The memory section is associated with a control-gate controller, a data-latch circuit, a sense amplifier section, and a data comparator, which is connected via an output buffer to a verify-termination detector. When a data is once written into a selected memory cell in a data programming mode, a specific basing voltage is applied to the selected cell so that the actual electrical data write condition of the selected memory cell is verified. If the comparator detects that the verified write condition is dissatisfied, data-rewriting operations are repeatedly executed by additionally supplied the selected cell with a suitable voltage which compensates for the dissatisfaction of the verified write condition in the selected memory cell transistor.

摘要翻译： NAND单元型电可擦除可编程只读存储器具有包含NAND单元单元的存储器阵列部分。 每个NAND单元单元具有作为存储单元晶体管的浮栅型金属氧化物半导体场效应晶体管的串联阵列。 存储器部分与控制门控制器，数据锁存电路，读出放大器部分和数据比较器相关联，其经由输出缓冲器连接到验证终止检测器。 当在数据编程模式中将数据一次写入所选择的存储单元中时，将特定的基准电压施加到所选择的单元，以便验证所选存储单元的实际电数据写入条件。 如果比较器检测到验证的写入条件不满意，则通过用选择的存储单元晶体管补偿所验证的写入条件的不满足的适当电压来额外提供所选择的单元来重复执行数据重写操作。

公开(公告)号：US5812455A

公开(公告)日：1998-09-22

申请号：US706434

申请日：1996-08-30

申请人： Yoshihisa Iwata ,  Hideko Oodaira

发明人： Yoshihisa Iwata ,  Hideko Oodaira

IPC分类号： H01L21/66 ,  G11C16/06 ,  G11C16/30 ,  G11C17/00 ,  H01L29/78

CPC分类号： G11C16/30

摘要： A NAND EEPROM is disclosed which is capable of variously setting, for each chip, the voltage to be applied to the control gates of memory cells. The semiconductor chip includes a NAND memory cell array and a high-voltage generating circuit for generating data writing internal voltage VPP required when data is written on the memory cell array. Moreover, the semiconductor chip includes a set voltage selection circuit for arbitrarily setting the level of the voltage VPP generated by the high-voltage generating circuit for each chip and a multiplexer for extracting, to the outside of the chip, setting signal LTF which is a signal for enabling the level of the voltage VPP set arbitrarily.

公开(公告)号：US5812451A

公开(公告)日：1998-09-22

申请号：US856800

申请日：1997-05-15

申请人： Yoshihisa Iwata

发明人： Yoshihisa Iwata

IPC分类号： H01L21/8247 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/3486 ,  G11C16/10 ,  G11C16/3459 ,  G11C16/3468

摘要： A semiconductor storage apparatus and a method of writing data to the semiconductor storage apparatus can restrict the threshold value of the memory cells, to which data has been written or from which data has been erased, to be included in a predetermined range without excessive writing by performing a verifying operation. In the writing operation, writing is performed such that a first determining level is set to a loose level which is the same as the level set for the reading operation or higher than the loose level but lower than a finally required determining level. In accordance with the first determining level, a first writing operation is performed. Then, a second writing operation is performed in accordance with a second determining level. The threshold value of a memory cell having a threshold value between the first determining level, which is the loose level, and the second determining level which is the required determining level (an aimed determining level) is raised to be higher than the second determining level, that is, the writing operation is performed by two steps. When the width of the distribution of the threshold values is reduced, data can reliably be erased from all of the memory cells when data is collectively erased in the erasing operation.

摘要翻译： 半导体存储装置和向半导体存储装置写入数据的方法可以将已经写入数据或从哪个数据被擦除的存储单元的阈值限制为包含在预定范围内而不会过度写入 执行验证操作。 在写入操作中，执行写入，使得第一确定级别被设置为与为读取操作设置的级别相同或高于松开级别但低于最终所需的确定级别的松开级别。 根据第一确定级别，执行第一写入操作。 然后，根据第二确定级别执行第二写入操作。 具有作为松散级的第一判定级之间的阈值和作为所需判定级别的第二判定级别（目标判定级别）的存储单元的阈值被提高到高于第二判定级别 也就是说，写入操作通过两个步骤执行。 当减少阈值分布的宽度时，在擦除操作中共同地擦除数据时，可以从所有存储单元可靠地擦除数据。

公开(公告)号：US5740112A

公开(公告)日：1998-04-14

申请号：US583533

申请日：1996-01-04

申请人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

发明人： Tomoharu Tanaka ,  Yoshiyuki Tanaka ,  Kazunori Ohuchi ,  Masaki Momodomi ,  Yoshihisa Iwata ,  Koji Sakui ,  Shinji Saito ,  Hideki Sumihara

IPC分类号： G11C7/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C7/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454 ,  G11C7/067

摘要： A sense amplifier for signal detection for use in an electrically erasable and programmable read-only memory (EEPROM). The sense amplifier includes a first clock signal-synchronized inverter including a first inverter and first switch for switching between activating and deactivating states of the first inverter, the first clock signal-synchronized inverter having a first input connected to a corresponding one of the bit lines and a first output. A second clock signal-synchronized inverter is arranged in parallel with the first clock signal-synchronized inverter and includes a second inverter and a second switch for switching between activating and deactivating states of the second inverter, the second clock signal-synchronized inverter having an input connected to the output of the first clock signal-synchronized inverter and an output connected to the input of the first clock signal-synchronized inverter. The switches in the first and second clock signal-synchronized inverters are activated with a delay so that a potential on the corresponding bit line is reliably sensed and latched at the output of the first clock signal-synchronized inverter.

摘要翻译： 用于电可擦除和可编程只读存储器（EEPROM）中的信号检测用读出放大器。 读出放大器包括：第一时钟信号同步反相器，包括第一反相器和用于在第一反相器的激活和去激活状态之间切换的第一开关，第一时钟信号同步反相器具有连接到对应的一个位线的第一输入 和第一个输出。 第二时钟信号同步反相器与第一时钟信号同步反相器并联布置，并且包括第二反相器和用于在第二反相器的激活和去激活状态之间切换的第二开关，第二时钟信号同步反相器具有输入 连接到第一时钟信号同步反相器的输出端，以及连接到第一时钟信号同步反相器的输入端的输出端。 第一和第二时钟信号同步反相器中的开关被延迟激活，使得对应位线上的电位被可靠地感测并锁存在第一时钟信号同步反相器的输出端。

公开(公告)号：US5726882A

公开(公告)日：1998-03-10

申请号：US659229

申请日：1996-06-05

申请人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

发明人： Junichi Miyamoto ,  Yasuo Itoh ,  Yoshihisa Iwata

IPC分类号： G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C16/02 ,  G11C16/06 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/3459 ,  G11C16/10 ,  G11C16/3454 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/1048

摘要： A non-volatile semiconductor memory device includes a flip-flop circuit for holding write data in one of first and second states. A bit line is connected to the flip-flop circuit via a switching element and a transistor charges the bit line. A non-volatile memory cell, connected to the bit line and having a MOS transistor structure, stores data when a threshold thereof is set in one of first and second threshold ranges, wherein at the time of a write mode the threshold of the memory cell is shifted from the first threshold range towards the second threshold range while the flip-flop circuit remains in the first state and the shift of the threshold is not effected while the flip-flop circuit remains in the second state, and at the time of a verify mode following the write mode the bit line is kept at a charge potential by the charging transistor while the threshold remains in the second threshold range. A data setting circuit connects one of first and second signal nodes of the flip-flop circuit to a predetermined potential when the bit line is at the charge potential in the verify mode, thereby setting the flip-flop circuit in the second state irrespective of the state prior to the verify mode.

摘要翻译： 非挥发性半导体存储器件包括用于保持第一和第二状态之一的写入数据的触发器电路。 位线通过开关元件连接到触发器电路，并且晶体管对位线进行充电。 连接到位线并具有MOS晶体管结构的非易失性存储单元将其阈值设置在第一和第二阈值范围中的一个时存储数据，其中在写入模式时，存储单元的阈值 在触发器电路保持在第一状态的同时触发器电路保持在第二状态，并且当触发器电路保持在第二状态时阈值的偏移不被影响时，从第一阈值范围向第二阈值范围移位， 在写模式之后，当阈值保持在第二阈值范围内时，位线被充电晶体管保持在电荷电位。 数据设定电路在检测模式中位线处于充电电位时，将触发器电路的第一和第二信号节点之一连接到预定电位，从而将触发器电路设置为第二状态，而与 在验证模式之前的状态。

公开(公告)号：US5657270A

公开(公告)日：1997-08-12

申请号：US376665

申请日：1995-01-23

申请人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

发明人： Kazunori Ohuchi ,  Tomoharu Tanaka ,  Yoshihisa Iwata ,  Yasuo Itoh ,  Masaki Momodomi ,  Fujio Masuoka

IPC分类号： G11C17/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/00 ,  G11C29/12 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/06

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device including a plurality of bit lines; a plurality of word lines insulatively intersecting the bit lines; a memory cell array including a plurality of memory cells coupled to the bit lines and the word lines, each memory cell including a transistor with a charge storage portion; a plurality of programming circuits coupled to the memory cell array (i) for storing data which define whether or not write voltages are to be applied to respective of the memory cells, (ii) for selectively applying the write voltages to a part of the memory cells, which part is selected according to the data stored in the plurality of programing circuits, (iii) for determining actual written states of the memory cells, and (iv) for selectively modifying the stored data based on a predetermined logical relationship between the determined actual written states of the memory cells and the data stored in the plurality of programming circuits, thereby applying the write voltages only to memory cells which are not sufficiently written to achieve a predetermined written state.

摘要翻译： 一种包括多个位线的非易失性半导体存储器件; 多个字线与位线绝对相交; 包括耦合到位线和字线的多个存储单元的存储单元阵列，每个存储单元包括具有电荷存储部分的晶体管; 耦合到存储单元阵列（i）的多个编程电路，用于存储定义是否将写入电压施加到存储单元的相应数据的数据，（ii）用于选择性地将写入电压施加到存储器的一部分 单元，根据存储在多个编程电路中的数据选择该部分，（iii）用于确定存储单元的实际写入状态，以及（iv）基于所确定的预定逻辑关系来选择性地修改所存储的数据 存储单元的实际写入状态和存储在多个编程电路中的数据，从而将写入电压仅施加到未被充分写入以实现预定写入状态的存储单元。

公开(公告)号：US5388084A

公开(公告)日：1995-02-07

申请号：US128087

申请日：1993-09-29

申请人： Yasuo Itoh ,  Sumio Tanaka ,  Junichi Miyamoto ,  Hiroshi Nakamura ,  Yoshihisa Iwata ,  Kenichi Imamiya ,  Yoshihisa Sugiura

发明人： Yasuo Itoh ,  Sumio Tanaka ,  Junichi Miyamoto ,  Hiroshi Nakamura ,  Yoshihisa Iwata ,  Kenichi Imamiya ,  Yoshihisa Sugiura

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C5/147 ,  G11C16/30

摘要： Disclosed is a semiconductor integrated circuit device, which comprises a booster circuit for boosting a source voltage, a voltage limiter having one end connected to the output terminal of the booster circuit, for limiting the output voltage of the booster circuit to a given value, and a voltage setting circuit, connected to the other end of the voltage limiter, for arbitrarily adjusting a voltage at the other end of the voltage limiter. This design can keep the output voltage of the booster circuit at a constant level and can set that output voltage to an arbitrary voltage.

摘要翻译： 公开了一种半导体集成电路装置，其包括用于升压源极电压的升压电路，具有连接到升压电路的输出端子的一端的限压器，用于将升压电路的输出电压限制在给定值，以及 连接到限压器的另一端的电压设定电路，用于任意地调节限压器另一端的电压。 该设计可以将升压电路的输出电压保持在恒定电平，并可将该输出电压设置为任意电压。

公开(公告)号：US09070434B2

公开(公告)日：2015-06-30

申请号：US13607529

申请日：2012-09-07

申请人： Takeshi Hioka ,  Yoshihisa Iwata

发明人： Takeshi Hioka ,  Yoshihisa Iwata

IPC分类号： G11C7/22 ,  G11C5/06 ,  G11C5/14 ,  G11C16/10

CPC分类号： G11C7/222 ,  G11C5/063 ,  G11C5/145 ,  G11C16/10

摘要： A semiconductor device comprises a stacked layer memory block and associated peripheral circuits, such as a booster circuit, in stacked layer arrangements. The booster circuit includes plural rectifier cells that are series-connected and plural first capacitors. The plural first capacitors receive a first clock signal on one end, and the other ends thereof are each connected to one end of a different rectifier cell. Each first capacitor is composed of plural first conductive layers that are arrayed with a set pitch perpendicular to the substrate. Either the even numbered or the odd numbered first conductive layers are supplied with the first clock signal. The other of the even numbered or odd numbered first conductive layers are each individually connected to one end of a different rectifier cell.

摘要翻译： 半导体器件包括堆叠层存储块和相关联的外围电路，例如叠层层布置中的升压电路。 升压电路包括串联连接的多个整流单元和多个第一电容器。 多个第一电容器在一端接收第一时钟信号，并且其另一端分别连接到不同整流器单元的一端。 每个第一电容器由垂直于衬底的设定间距排列的多个第一导电层组成。 偶数或奇数的第一导电层被提供有第一时钟信号。 偶数或奇数编号的第一导电层中的另一个分别连接到不同整流器单元的一端。

公开(公告)号：US08853766B2

公开(公告)日：2014-10-07

申请号：US13275436

申请日：2011-10-18

申请人： Takashi Maeda ,  Yoshihisa Iwata

发明人： Takashi Maeda ,  Yoshihisa Iwata

IPC分类号： H01L29/792 ,  H01L27/115

CPC分类号： H01L23/528 ,  H01L23/5226 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a nonvolatile semiconductor memory device, a stacked body is formed by alternately stacking dielectric films and conductive films on a silicon substrate and a plurality of through holes extending in the stacking direction are formed in a matrix configuration. A shunt interconnect and a bit interconnect are provided above the stacked body. Conductor pillars are buried inside the through holes arranged in a line immediately below the shunt interconnect out of the plurality of through holes, and semiconductor pillars are buried inside the remaining through holes. The conductive pillars are formed from a metal, or low resistance silicon. Its upper end portion is connected to the shunt interconnect and its lower end portion is connected to a cell source formed in an upper layer portion of the silicon substrate.

摘要翻译： 在非易失性半导体存储器件中，通过在硅衬底上交替堆叠电介质膜和导电膜来形成层叠体，并且以矩阵形式形成沿堆叠方向延伸的多个通孔。 分路互连和位互连设置在堆叠体的上方。 导体支柱埋设在多个通孔中的分流互连的正下方配置的贯通孔的内侧，半导体柱埋设在剩余通孔的内部。 导电柱由金属或低电阻硅形成。 其上端部连接到分路互连，并且其下端部连接到形成在硅衬底的上层部分中的电池源。