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公开(公告)号:US11800266B2
公开(公告)日:2023-10-24
申请号:US17332148
申请日:2021-05-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Ioannis (Giannis) Patronas , Paraskevas Bakopoulos , Elad Mentovich , Barak Gafni , Adam V. Richards
CPC classification number: H04Q11/0071 , H04L45/04 , H04Q11/0005 , H04Q2011/009 , H04Q2011/0052 , H04Q2213/003 , H04Q2213/322
Abstract: A device for a network switch comprises N input ports, and an electrical block including a plurality of electrical switches configured to route signals in an electrical domain. Each electrical switch includes M input ports, and the device further comprises an optical block coupled to the electrical block. The optical block is configured to route signals in an optical domain. A configuration of the optical block and a configuration of the electrical block are based on at least a number of the N input ports.
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公开(公告)号:US11789203B2
公开(公告)日:2023-10-17
申请号:US17362405
申请日:2021-06-29
Applicant: Mellanox Technologies, Ltd.
Inventor: Dimitrios Kalavrouziotis , Yaakov Gridish , Paraskevas Bakopoulos , Anders Gösta Larsson , Elad Mentovich
CPC classification number: G02B6/268 , G02B6/262 , G02B6/421 , G02B6/1228 , G02B6/14 , H01S3/06745
Abstract: Embodiments are disclosed for a coupling element with embedded modal filtering for a laser and/or a photodiode. An example system includes a laser and an optical coupling element. The laser is configured to emit an optical signal. The optical coupling element is configured to receive the optical signal emitted by the laser. The optical coupling element is also configured to be connected to an optical fiber such that, in operation, the optical signal is transmitted from the laser to the optical fiber via the optical coupling element. Furthermore, the coupling element comprises a tapered section that provides modal filtering of the optical signal.
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公开(公告)号:US20230305250A1
公开(公告)日:2023-09-28
申请号:US17660348
申请日:2022-04-22
Applicant: Mellanox Technologies, Ltd.
Inventor: Elad Mentovich , Paraskevas Bakopoulos , Boaz Atias , Anna Sandomirsky , James Steven Fields, JR. , Dimitrios Kalavrouziotis
Abstract: An optoelectronic component may include a substrate, an electronic integrated circuit supported by the substrate, and a photonic integrated circuit supported by the substrate. The optoelectronic component may include a plurality of substrate interconnect connectors disposed on the substrate, a plurality of electronic integrated circuit interconnect connectors disposed on the electronic integrated circuit, and a plurality of photonic integrated circuit interconnect connectors disposed on the photonic integrated circuit. The optoelectronic component may include a first plurality of cable connectors, each cable connector connected to the substrate, the electronic integrated circuit, and the photonic integrated circuit via respective interconnect connectors. The first plurality of cable connectors may be configured to facilitate electrical communication between the substrate, the electronic integrated circuit, and the photonic integrated circuit. The first plurality of cable connectors may define a first layout, and an overall connectivity of the optoelectronic component may correspond to the first layout.
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公开(公告)号:US11769989B2
公开(公告)日:2023-09-26
申请号:US17249224
申请日:2021-02-24
Applicant: Mellanox Technologies, Ltd.
Inventor: Yuri Berk , Vladimir Iakovlev , Isabelle Cestier , Elad Mentovich
CPC classification number: H01S5/34306 , H01S5/021 , H01S5/18308 , H01S5/18366 , H01S5/2086 , H01S5/3095 , H01S5/068 , H01S5/18344 , H01S5/3416 , H01S5/34313 , H01S5/34366
Abstract: VCSELs designed to emit light at a characteristic wavelength in a wavelength range of 910-2000 nm and formed on a silicon substrate are provided. Integrated VCSEL systems are also provided that include one or more VCSELs formed on a silicon substrate and one or more electrical, optical, and/or electro-optical components formed and/or mounted onto the silicon substrate. In an integrated VCSEL system, at least one of the one or more electrical, optical, and/or electro-optical components formed and/or mounted onto the silicon substrate is electrically or optically coupled to at least one of the one or more VSCELs on the silicon substrate. Methods for fabricating VCSELs on a silicon substrate and/or fabricating an integrated VCSEL system are also provided.
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公开(公告)号:US11765237B1
公开(公告)日:2023-09-19
申请号:US17724540
申请日:2022-04-20
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Liran Liss , Yamin Friedman , Michael Kagan , Diego Crupnicoff , Idan Burstein , Matty Kadosh , Tzah Oved , Dror Goldenberg , Ron Yuval Efraim , Alexander Eli Rosenbaum , Aviad Yehezkel , Rabia Loulou
IPC: H04L67/141 , H04L67/146 , G06F15/173 , H04L69/16 , H04L9/08
CPC classification number: H04L67/141 , G06F15/17331 , H04L9/0825 , H04L67/146 , H04L69/161
Abstract: Apparatus for data communication includes a network interface for connection to a packet data network and a host interface for connection to a host computer, which includes a central processing unit (CPU) and a host memory. Packet processing circuitry receives, via the host interface, from a kernel running on the CPU, associations between multiple remote direct memory access (RDMA) sessions and multiple different User Datagram Protocol (UDP) 5-tuple, which are assigned respectively to the RDMA sessions, and receives from an application running on the CPU a request to send an RDMA message, using a selected group of one or more of the RDMA sessions, to a peer application over the packet data network, and in response to the request, transmits, via the network interface, one or more data packets using a UDP 5-tuple that is assigned to one of the RDMA sessions in the selected group.
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公开(公告)号:US20230291693A1
公开(公告)日:2023-09-14
申请号:US17588295
申请日:2022-01-30
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Gal Yefet , Saar Tarnopolsky , Avi Urman , Dotan David Levi , Elena Agostini
IPC: H04L47/2441 , H04L69/22
CPC classification number: H04L47/2441 , H04L69/22
Abstract: In one embodiments, data communication system include a communication apparatus, which is configured to receive data from different user equipment devices a schedule of time periods, and packetize the data from respective ones of the user equipment devices for respective ones of the time periods into packets, a memory including a plurality of buffers, and a network interface controller configured to receive the packets from the communication apparatus, and scatter respective portions of the data belonging to respective groups of successive ones of the time periods to the buffers, responsively to a static set of steering rules, and timing information of respective ones of the packets, and wherein each respective portion of the data is scattered to the buffers a same scatter pattern.
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公开(公告)号:US11741232B2
公开(公告)日:2023-08-29
申请号:US17163599
申请日:2021-02-01
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Mor Hoyda Sfadia , Yuval Itkin , Ahmad Atamli , Ariel Shahar , Yaniv Strassberg , Itsik Levi
CPC classification number: G06F21/572 , G06F8/65 , G06F9/445 , G06F2221/033
Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.
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公开(公告)号:US11740985B2
公开(公告)日:2023-08-29
申请号:US17241079
申请日:2021-04-27
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Ran Koren , Shay Aisman , Itamar Rabenstein , Amir Ancel
IPC: G06F11/273 , G06F13/20 , G06F11/22 , G06F11/34 , G06F11/30
CPC classification number: G06F11/273 , G06F11/2268 , G06F11/3072 , G06F11/3075 , G06F11/3476 , G06F11/3485 , G06F13/20 , G06F11/3013 , G06F11/348
Abstract: An apparatus includes operational circuitry and Hardware Diagnostics Circuitry (HDC). The HDC is configured to receive a definition of multiple trigger rules, each trigger rule specifying a respective trigger event as a function of trigger data sources in the operational circuitry, to receive a definition of (i) a pre-trigger logging set selected from among a plurality of diagnostics data sources in the operational circuitry, and (ii) for each trigger rule, a respective post-trigger logging set including a set of one or more of the diagnostics data sources, and, during operation of the operational circuitry, to log the diagnostics data sources in the pre-trigger logging set, to log the trigger data sources and to repeatedly evaluate the trigger rules, and, in response to triggering of a given trigger event by a given trigger rule, to start logging the diagnostics data sources in the post-trigger logging set of the given trigger rule.
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公开(公告)号:US20230269684A1
公开(公告)日:2023-08-24
申请号:US17675548
申请日:2022-02-18
Applicant: MELLANOX TECHNOLOGIES, LTD.
Inventor: Wojciech Wasko , Dotan David Levi , Natan Manevich , Timothy James Martin
IPC: H04W56/00
CPC classification number: H04W56/0045
Abstract: A network adapter comprises an output that couples to a central processing unit (CPU) of a network device, a first clock coupled to the output and configured to be synchronized with a second clock that is external to the CPU and the network adapter, and circuitry coupled to the first clock. The circuitry is configured to generate, using the synchronized first clock, a tick at a time offset from a timeslot of a radio schedule for a radio unit and send the tick to the output.
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公开(公告)号:US20230269077A1
公开(公告)日:2023-08-24
申请号:US17683972
申请日:2022-03-01
Applicant: MELLANOX TECHNOLOGIES, LTD.
CPC classification number: H04L9/0825 , H04L9/0838 , H04L9/0852 , H04L9/3236
Abstract: Systems, data processing systems, and methods, among other things, are disclosed. An illustrative system includes an encryption orchestrator that analyzes a packet, obtains a tenant identifier (ID) from the packet, determines whether a tenant associated with the tenant ID currently has sufficient encryption credit available, and enables an encryption resource to process the packet using an encryption key associated with the tenant ID in response to determining that the tenant associated with the tenant ID currently has sufficient encryption credit available.
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