公开(公告)号：US12230316B2

公开(公告)日：2025-02-18

申请号：US18412380

申请日：2024-01-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Atuk Katoch

IPC: G11C5/14 ,  G11C11/417 ,  H10B10/00

Abstract: A memory device including memory cells and edge cells is described. In one example, the memory device includes: an array of memory cells used for data storage; a plurality of first edge cells not used for data storage; and a plurality of second edge cells not used for data storage. The plurality of first edge cells and the plurality of second edge cells are arranged respectively at two opposite sides of the array of memory cells. At least one edge cell, among the plurality of first edge cells and the plurality of second edge cells, comprises a circuit configured for controlling the array of memory cells to enter or exit a power down mode.

公开(公告)号：US12228768B2

公开(公告)日：2025-02-18

申请号：US18063186

申请日：2022-12-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Weiwei Song ,  Chan-Hong Chern ,  Chih-Chang Lin ,  Stefan Rusu ,  Min-Hsiang Hsu

IPC: G02B6/124 ,  B29D11/00 ,  G02B6/122 ,  G02B6/132 ,  G02B6/12

Abstract: Methods of fabricating optical devices with high refractive index materials are disclosed. The method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.

公开(公告)号：US20250056866A1

公开(公告)日：2025-02-13

申请号：US18447802

申请日：2023-08-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jhon-Jhy LIAW

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/775

Abstract: A semiconductor device includes circuit cells having transistors. Each of the transistors includes nanostructures vertically stacked from each other in a Z-direction, a gate structure wrapping around the nanostructures and extending in a Y-direction, and source/drain features on opposite sides of the gate structure in an X-direction. The semiconductor device further includes silicide features over and in contact with the source/drain features. The silicide features extend lower than bottom surfaces of topmost nanostructures of the nanostructures. The semiconductor device further includes source/drain contacts over and in contact with the silicide features. Each of bottom surfaces of the source/drain contacts has a V-shape in an X-Z cross-sectional view.

公开(公告)号：US20250056823A1

公开(公告)日：2025-02-13

申请号：US18931886

申请日：2024-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsu-Hui Su ,  Chun-Hsiang Fan ,  Yu-Wen Wang ,  Ming-Hsi Yeh ,  Kuo-Bin Huang

IPC: H01L29/66 ,  H01L21/306 ,  H01L21/66 ,  H01L21/762 ,  H01L21/8238

Abstract: A method includes forming isolation regions extending into a semiconductor substrate. A semiconductor strip is between the isolation regions. The method further includes recessing the isolation regions so that a top portion of the semiconductor strip protrudes higher than top surfaces of the isolation regions to form a semiconductor fin, measuring a fin width of the semiconductor fin, generating an etch recipe based on the fin width, and performing a thinning process on the semiconductor fin using the etching recipe.

公开(公告)号：US20250054765A1

公开(公告)日：2025-02-13

申请号：US18932462

申请日：2024-10-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan YOU ,  Chia-Hao CHANG ,  Chu-Yuan HSU ,  Kuo-Cheng CHIANG ,  Chih-Hao WANG

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: An integrated circuit includes a first nanostructure transistor having a first gate electrode and a second nanostructure transistor having a second gate electrode. A dielectric isolation structure is between the first and second gate electrodes. A gate connection metal is on a portion of the top surface of the first gate electrode and on a portion of a top surface of the second gate electrode. The gate connection metal is patterned to expose other portions of the top surfaces of the first and second gate electrodes adjacent to the dielectric isolation structure. A conductive via contacts the exposed portion of the top surface of the second gate electrode.

公开(公告)号：US20250053064A1

公开(公告)日：2025-02-13

申请号：US18448337

申请日：2023-08-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Su-Chun Yang ,  Chen Chiang Yu ,  Jui Hsuan Tsai ,  Jih-Churng Twu ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: G02F1/355 ,  G02F1/35

Abstract: Optical devices and methods of manufacture are presented in which a non-linear material is deposited or otherwise placed. Once the non-linear material has been deposited, implantation regions are formed within the non-linear material using an implantation process. The implantation regions are removed using an etching process, and electrodes are formed to the remaining material.

公开(公告)号：US12225734B2

公开(公告)日：2025-02-11

申请号：US17815000

申请日：2022-07-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Shy-Jay Lin ,  Mingyuan Song ,  Hiroki Noguchi

IPC: H10B61/00 ,  H01L29/78 ,  H10N50/01 ,  H10N50/80

Abstract: A method includes depositing a first dielectric layer over a semiconductor substrate, depositing a first electrode layer over the first dielectric layer, etching the first electrode layer to form a first electrode and a second electrode laterally separated from the first electrode, depositing a Spin Orbit Torque (SOT) material on the first electrode and the second electrode, depositing Magnetic Tunnel Junction (MTJ) layers on the SOT material, depositing a second electrode layer on the MTJ layers, etching the SOT material to form a SOT layer extending from the first electrode to the second electrode, etching the MTJ layers to form an MTJ stack on the SOT layer, and etching the second electrode layer to form a top electrode on the MTJ stack.

公开(公告)号：US12224327B2

公开(公告)日：2025-02-11

申请号：US18366369

申请日：2023-08-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Ju Chen ,  Shih-Hsiang Chiu ,  Su-Hao Liu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/40 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

Abstract: Methods for improving sealing between contact plugs and adjacent dielectric layers and semiconductor devices formed by the same are disclosed. In an embodiment, a semiconductor device includes a first dielectric layer over a conductive feature, a first portion of the first dielectric layer including a first dopant; a metal feature electrically coupled to the conductive feature, the metal feature including a first contact material in contact with the conductive feature; a second contact material over the first contact material, the second contact material including a material different from the first contact material, a first portion of the second contact material further including the first dopant; and a dielectric liner between the first dielectric layer and the metal feature, a first portion of the dielectric liner including the first dopant.

公开(公告)号：US12224325B2

公开(公告)日：2025-02-11

申请号：US18353027

申请日：2023-07-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L21/768 ,  H01L27/088 ,  H01L27/092 ,  H01L29/40 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/8234

Abstract: A method includes forming a dummy gate structure over a substrate; forming a source/drain structure over the substrate; replacing the dummy gate structure with a metal gate structure; forming a protection cap over the metal gate structure; forming a source/drain contact over the source/drain structure; performing a selective deposition process to form a first etch stop layer on the protection cap, in which the selective deposition process has a faster deposition rate on the protection cap than on the source/drain contact; depositing a second etch stop layer over the first etch stop layer the source/drain contact; etching the second etch stop layer to form an opening; and forming a via contact in the opening.

公开(公告)号：US12224213B2

公开(公告)日：2025-02-11

申请号：US17008251

申请日：2020-08-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sung-Hsin Yang ,  Jung-Chi Jeng ,  Ru-Shang Hsiao

IPC: H01L21/8234 ,  H01L21/027 ,  H01L21/308 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H03M1/06

Abstract: Semiconductor devices and methods are provided. A semiconductor device according to the present disclosure includes a substrate having a first area and a second area, a plurality of fin structures extending along a direction over the first area and the second area of the substrate, a first transistor and a second transistor in the first area, a first isolation structure disposed between the first transistor and the second transistor, a first isolation structure disposed between the first transistor and the second transistor, a third transistor and a fourth transistor in the second area, and a second isolation structure disposed between the third transistor and the fourth transistor. The first isolation structure includes a first width along the direction and the second isolation structure includes a second width along the direction. The second width is greater than the first width.