公开(公告)号：US11651807B2

公开(公告)日：2023-05-16

申请号：US17113595

申请日：2020-12-07

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Yaojun Zhang ,  Frederick Neumeyer

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1659 ,  G11C11/1657

Abstract: The present disclosure is drawn to a magnetoresistive device including an array of memory cells arranged in rows and columns, each memory cell comprising a magnetic tunnel junction, each row comprising a word line, and each column comprising a bit line; a column select device that selects a bit line. The magnetoresistive device also includes a sense amplifier comprising a first input corresponding to a selected bit line, a second input corresponding to a reference bit line, and a data output. The plurality of columns comprise a reference column, the reference column comprising a conductive element coupled to the magnetic tunnel junctions in the reference column.

公开(公告)号：US10446213B1

公开(公告)日：2019-10-15

申请号：US15980977

申请日：2018-05-16

Applicant: Everspin Technologies Inc.

Inventor： Yaojun Zhang ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/00 ,  G11C11/16

Abstract: The present disclosure is drawn to, among other things, a magnetoresistive memory. The magnetoresistive memory includes a first memory cell, a first access circuit, a second access circuit, and a current generating circuit. The first memory cell includes a first magnetic tunnel junction and a second magnetic tunnel junction. The first access circuit is configured to receive access command signals for accessing the first magnetic tunnel junction. The first access circuit includes a first access switch and a second access switch. The second access circuit is configured to receive access command signals for accessing the second magnetic tunnel junction. The second access circuit includes a third access switch and a fourth access switch. The current generating circuit is configured to generate a first write current through the first magnetic tunnel junction and generate a second write current through the second magnetic tunnel junction based on data input signals.

公开(公告)号：US10256840B2

公开(公告)日：2019-04-09

申请号：US15385130

申请日：2016-12-20

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: H03M13/00 ,  H03M13/29 ,  G06F11/10

Abstract: A memory device includes memory arrays configured to store pages of data organized into multiple ECC words. The memory device also includes at least one input/output pad for each ECC word associated with a page. The memory device is configurable to perform a first level of error correction on each of the ECC words associated with the page. A system-level error correction circuit is configurable to perform a second level of error correction on the data output by each of the input/output pads during a particular period of time. Each of the one or more input/output pads of the memory device is configurable to provide only one bit of data per ECC word to an external source during an access from an external source.

公开(公告)号：US10249364B2

公开(公告)日：2019-04-02

申请号：US15840214

申请日：2017-12-13

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Yaojun Zhang

IPC: G11C11/56 ,  G11C11/16 ,  H01L43/12 ,  G11C11/419 ,  H01L27/11 ,  H01L43/02 ,  H01L43/08 ,  G11C13/00

Abstract: Higher word line voltages facilitate write operations in spin-torque magnetic memory devices, but overdriving the gate of a selection transistor with such higher word line voltages can damage the selection transistor if the gate-to-source voltage for the selection transistor is too high. Therefore in order to support the word line voltage needed on the gate of the select transistor for an up-current write operation without exceeding limits on the gate-to-source voltage for the select transistor, the gate of the selection transistor can be driven in a two-step process. The gate of the selection transistor is first driven to a lower voltage within the limits of the gate-to-source voltage for the transistor when the source of the transistor is grounded or at a voltage near ground. A voltage is then applied across the memory cell, which results in the source of the selection transistor being raised above its initial ground or near-ground state. After the source of the selection transistor has been raised, the gate voltage of the selection transistor can also be raised at least as much as the source of the selection transistor has been elevated without violating the limits on the gate-to-source voltage for the selection transistor.

公开(公告)号：US20180342276A1

公开(公告)日：2018-11-29

申请号：US16000071

申请日：2018-06-05

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. Alam ,  Chitra Subramanian

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1675 ,  G11C27/024

Abstract: Precharging circuits and techniques are presented for use with magnetic memory devices in order to speed up access to the memory cells for reading and writing. Including precharging in the sense amplifiers used to access the memory cells enables self-referenced read operations to be completed more quickly than is possible without precharging. Similarly, precharging can also be used in conjunction with write-back operations in order to allow the data state stored by magnetic tunnel junctions included in the memory cells to be changed more rapidly.

公开(公告)号：US09997239B1

公开(公告)日：2018-06-12

申请号：US15584232

申请日：2017-05-02

Applicant: EVERSPIN TECHNOLOGIES, INC.

Inventor： Syed M. Alam ,  Yaojun Zhang

IPC: G11C11/16 ,  G11C11/56 ,  G11C11/419 ,  H01L27/11 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/12 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1675 ,  G11C11/1693 ,  G11C2013/0071 ,  H01L27/11

Abstract: Higher word line voltages facilitate write operations in spin-torque magnetic memory devices, but overdriving the gate of a selection transistor with such higher word line voltages can damage the selection transistor if the gate-to-source voltage for the selection transistor is too high. Therefore in order to support the word line voltage needed on the gate of the select transistor for an up-current write operation without exceeding limits on the gate-to-source voltage for the select transistor, the gate of the selection transistor can be driven in a two-step process. The gate of the selection transistor is first driven to a lower voltage within the limits of the gate-to-source voltage for the transistor when the source of the transistor is grounded or at a voltage near ground. A voltage is then applied across the memory cell, which results in the source of the selection transistor being raised above its initial ground or near-ground state. After the source of the selection transistor has been raised, the gate voltage of the selection transistor can also be raised at least as much as the source of the selection transistor has been elevated without violating the limits on the gate-to-source voltage for the selection transistor.

公开(公告)号：US09847116B2

公开(公告)日：2017-12-19

申请号：US15369246

申请日：2016-12-05

Applicant: Everspin Technologies, Inc.

Inventor： Dietmar Gogl ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/16 ,  G11C13/00 ,  G11C5/14

CPC classification number: G11C11/1675 ,  G11C5/147 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1697 ,  G11C13/0069 ,  G11C2213/79

Abstract: A cell bias control circuit maximizes the performance of devices in the read/write path of memory cells (magnetic tunnel junction device+transistor) without exceeding leakage current or reliability limits by automatically adjusting multiple control inputs of the read/write path at the memory array according to predefined profiles over supply voltage, temperature, and process corner variations by applying any specific reference parameter profiles to the memory array.

公开(公告)号：US09734884B2

公开(公告)日：2017-08-15

申请号：US15168166

申请日：2016-05-30

Applicant: Everspin Technologies, Inc.

Inventor： Syed M. Alam ,  Thomas Andre

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/15

CPC classification number: G11C11/1675 ,  G11C11/15 ,  G11C11/16 ,  G11C11/1653 ,  G11C11/1659 ,  G11C11/1673

Abstract: A method of applying a write current to a magnetic tunnel junction device minimizes sub-threshold leakage. NMOS- and PMOS-follower circuits are used in applying the write current, and bias signals for the follower circuits are isolated from global bias signals before the write current is applied.

公开(公告)号：US09569640B2

公开(公告)日：2017-02-14

申请号：US14832495

申请日：2015-08-21

Applicant: Everspin Technologies, Inc.

Inventor： Chitra K. Subramanian ,  Halbert S. Lin ,  Syed M. Alam ,  Thomas Andre

IPC: G11C11/00 ,  G11C5/14 ,  G06F21/79 ,  G11C7/24 ,  G11C11/16 ,  G06F21/60 ,  G11C13/00

CPC classification number: G06F21/79 ,  G06F21/60 ,  G11C7/14 ,  G11C7/24 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1695 ,  G11C13/0002 ,  G11C13/004 ,  G11C13/0059 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073

Abstract: A technique for detecting tampering attempts directed at a memory device includes setting each of a plurality of detection memory cells to an initial predetermined state, where corresponding portions of the plurality of detection memory cells are included in each of the arrays of data storage memory cells on the memory device. A plurality of corresponding reference bits on the memory device permanently store information representative of the initial predetermined state of each of the detection memory elements. When a tamper detection check is performed, a comparison between the reference bits and the current state of the detection memory cells is used to determine whether any of the detection memory cells have changed state from their initial predetermined states. Based on the comparison, a tamper detect indication is flagged if a threshold level of change is determined. Once a tampering attempt is detected, responses on the memory device include disabling one or more memory operations, generating a mock current to emulate current expected during normal operation, and erasing data stored on the memory device.

Abstract translation: 用于检测针对存储器件的篡改尝试的技术包括将多个检测存储器单元中的每一个设置为初始预定状态，其中多个检测存储器单元的相应部分被包括在每个数据存储单元阵列中 存储设备。 存储器装置上的多个对应的参考位永久地存储表示每个检测存储器元件的初始预定状态的信息。 当执行篡改检测检查时，使用检测存储单元的参考位与当前状态之间的比较来确定检测存储单元中的任何一个是否已经从其初始预定状态改变状态。 基于该比较，如果确定了阈值变化水平，则标记篡改检测指示。 一旦检测到篡改尝试，在存储器装置上的响应包括禁用一个或多个存储器操作，产生模拟电流以模拟在正常操作期间预期的电流，以及擦除存储在存储器件上的数据。

公开(公告)号：US09552849B2

公开(公告)日：2017-01-24

申请号：US14973884

申请日：2015-12-18

Applicant: Everspin Technologies, Inc.

Inventor： Thomas Andre ,  Syed M. Alam ,  Halbert S Lin

IPC: G11C7/00 ,  G11C11/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C11/1675 ,  G06F12/0802 ,  G06F2212/222 ,  G11C7/00 ,  G11C7/1042 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/4076

Abstract: In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.

Abstract translation: 在一些示例中，存储器设备被配置为接收预充电命令和激活命令。 响应于接收到所述预充电命令，响应于接收到所述激活命令，所述存储器装置执行与所述预充电命令相关的第一系列事件和与所述激活命令相关的第二系列事件。 存储器件延迟第二系列事件的开始直到第一系列事件完成。