公开(公告)号：US09852986B1

公开(公告)日：2017-12-26

申请号：US15362035

申请日：2016-11-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  Guillaume Bouche

IPC: H01L21/308 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/3081 ,  H01L21/3088 ,  H01L21/76843 ,  H01L21/76892

Abstract: A method including providing a semiconductor structure having a dielectric stack, hardmask stack, and mandrel layer disposed thereon. An array of mandrels is patterned into the mandrel layer. Mandrel spacers are formed self-aligned on sidewalls of the mandrels. A gapfill layer is disposed and planarized over the semiconductor structure. Non-mandrel pillars are formed over the planarized gapfill layer. Exposed portions of the gapfill layer are etched to form non-mandrel plugs preserved by the pillars. The pillars are removed to form a pattern, the pattern including the non-mandrel plugs. The pattern is utilized to form an array of alternating mandrel and non-mandrel metal interconnection lines in the dielectric stack. The array includes non-mandrel dielectric structures formed from the non-mandrel plugs.

公开(公告)号：US09818651B2

公开(公告)日：2017-11-14

申请号：US15067953

申请日：2016-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Tuhin Guha Neogi ,  Andy Chi-Hung Wei ,  Jia Zeng ,  Jongwook Kye ,  Jason Eugene Stephens ,  Irene Yuh-Ling Lin ,  Sudharshanan Raghunathan ,  Lei Yuan

IPC: H01L21/00 ,  H01L21/8238 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285 ,  H01L21/027 ,  H01L27/092 ,  H01L23/535 ,  G06F17/50

CPC classification number: H01L21/823871 ,  G06F17/5072 ,  H01L21/027 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/823821 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/0924

Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.

公开(公告)号：US09812400B1

公开(公告)日：2017-11-07

申请号：US15154367

申请日：2016-05-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Keith H. Tabakman ,  Patrick D. Carpenter ,  Guillaume Bouche ,  Michael V. Aquilino

IPC: H01L29/40 ,  H01L29/66 ,  H01L21/336 ,  H01L23/535 ,  H01L29/78 ,  H01L29/417 ,  H01L21/768

CPC classification number: H01L23/535 ,  H01L21/76816 ,  H01L21/76841 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a dielectric layer and providing electrical connection to source/drain epitaxial regions surrounding a set of fins, the contact line including: a first portion of the contact line electrically isolated from a second portion of the contact line by a contact line spacer, wherein the first portion and the second portion each include a liner layer and a metal, the liner layer separating the metal from the dielectric layer and the source/drain epitaxial regions, and wherein the metal is directly in contact with the contact line spacer.

公开(公告)号：US09779943B2

公开(公告)日：2017-10-03

申请号：US15053818

申请日：2016-02-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jason Eugene Stephens

IPC: H01L21/4763 ,  H01L21/033 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/0337 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228

Abstract: A hard mask is formed into lines and bridges two adjacent lines using mandrels, spacers for the mandrels and a lithographic process for each bridge to create a metal line pattern in a layer of an interconnect structure with a line pitch below lithographic resolution.

公开(公告)号：US20170221886A1

公开(公告)日：2017-08-03

申请号：US15490702

申请日：2017-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski ,  Tuhin Guha Neogi ,  Jason E. Stephens ,  Jongwook Kye ,  Jia Zeng

IPC: H01L27/088 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/088 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28568 ,  H01L21/76834 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823475 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/5329 ,  H01L27/092 ,  H01L29/41725 ,  H01L29/41758 ,  H01L29/66462 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved semiconductor structure and methods of fabrication that provide transistor contacts that are self-aligned in two dimensions. Two different capping layers are used, each being comprised of a different material. The two capping layers are selectively etchable to each other. One capping layer is used for gate coverage while the other capping layer is used for source/drain coverage. Selective etch processes open the desired gates and source/drains, while block masks are used to cover elements that are not part of the connection scheme. A metallization line (layer) is deposited, making contact with the open elements to provide electrical connectivity between them.

公开(公告)号：US09666488B1

公开(公告)日：2017-05-30

申请号：US15095612

申请日：2016-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tuhin Guha Neogi ,  David Pritchard ,  Scott Luning ,  Guillaume Bouche ,  David Doman

IPC: H01L21/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/285 ,  H01L27/092 ,  H01L27/12 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823864 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7838 ,  H01L29/7848

Abstract: A method of forming a silicide layer as a pass-through contact under a gate contact between p-epilayer and n-epilayer source/drains and the resulting device are provided. Embodiments include depositing a semiconductor layer over a substrate; forming a pFET gate on a p-side of the semiconductor layer and a nFET gate on a n-side of the semiconductor layer; forming a gate contact between the pFET gate and the nFET gate; forming raised source/drains on opposite sides of each of the pFET and nFET gates; and forming a metal silicide over a first raised source/drain on the p-side and over a second raised source/drain on the n-side, wherein the metal silicide extends from the first raised source/drain to the second raised source/drain and below the gate contact between the pFET and nFET gates.

公开(公告)号：US20170004999A1

公开(公告)日：2017-01-05

申请号：US15269138

申请日：2016-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy C. Wei ,  Sudharshanan Raghunthathan

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines are embedded in a second dielectric layer disposed above the first dielectric layer. A first conductive line in the first plurality of conductive lines contacts the conductive feature and includes a conductive via portion and a recessed line portion. A second plurality of conductive lines are embedded in a third dielectric layer disposed above the second dielectric layer. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the conductive via portion has a first cross-sectional dimension corresponding to a width of the first conductive line and a second cross-sectional dimension corresponding to a width of the second conductive line.

Abstract translation: 一种器件包括具有嵌入其中的至少一个导电特征的第一介电层。 第一多个导电线被嵌入设置在第一电介质层上方的第二电介质层中。 第一多个导电线中的第一导电线接触导电特征并且包括导电通路部分和凹陷线部分。 第二多个导电线被嵌入设置在第二电介质层上方的第三电介质层中。 第二多个导电线中的第二导线与导电通路部分接触，并且导电通路部分具有对应于第一导线的宽度的第一横截面尺寸和对应于第一导电线宽度的第二横截面尺寸 第二导线。

公开(公告)号：US09502293B2

公开(公告)日：2016-11-22

申请号：US14543992

申请日：2014-11-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy C. Wei ,  Sudharshanan Raghunthathan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76877 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a first dielectric layer having at least one conductive feature embedded therein. A first plurality of conductive lines embedded in a second dielectric layer disposed above the first dielectric layer is formed. A first conductive line in the plurality of conductive lines contacts the conductive feature. The first conductive line is etched using a first etch mask to define a conductive via portion and a recessed line portion in the first conductive line. A second plurality of conductive lines embedded in a third dielectric layer disposed above the second dielectric layer is formed. A second conductive line in the second plurality of conductive lines contacts the conductive via portion and the third dielectric layer directly contacts the second dielectric layer.

Abstract translation: 一种方法包括形成具有嵌入其中的至少一个导电特征的第一电介质层。 形成嵌入在设置在第一电介质层上方的第二电介质层中的第一多个导电线。 多个导线中的第一导线接触导电特征。 使用第一蚀刻掩模蚀刻第一导电线以在第一导电线中限定导电通路部分和凹陷线部分。 形成嵌入在第二电介质层上方的第三电介质层中的第二多个导电线。 第二多个导电线中的第二导线接触导电通路部分，第三电介质层直接接触第二电介质层。

公开(公告)号：US09490340B2

公开(公告)日：2016-11-08

申请号：US14308138

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao-Ming Koh ,  Guillaume Bouche ,  Jing Wan ,  Andy C. Wei

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/06 ,  H01L21/265 ,  H01L21/223

CPC classification number: H01L29/6653 ,  H01L21/2236 ,  H01L21/26586 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device.

Abstract translation: 形成纳米线器件的方法包括图案化多个半导体材料层，使得每个层具有第一和第二暴露的端表面。 该方法还包括在半导体材料层的第一和第二暴露的端表面中形成掺杂的延伸区域。 该方法还包括：在形成掺杂的延伸区域之后，在器件的源极和漏极区域中形成外延半导体材料。

公开(公告)号：US09460963B2

公开(公告)日：2016-10-04

申请号：US14225529

申请日：2014-03-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gabriel Padron Wells ,  Xiang Hu ,  Guillaume Bouche ,  Andre Labonte

IPC: H01L21/467 ,  H01L21/768 ,  H01L29/40 ,  H01L21/033 ,  H01L21/308 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/467 ,  H01L21/823431 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/401 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

Abstract: Embodiments of the present invention provide an improved contact and method of fabrication. A dielectric layer is formed over transistor structures which include gates and source/drain regions. A first etch, which may be a reactive ion etch, is used to partially recess the dielectric layer. A second etch is then used to continue the etch of the dielectric layer to form a cavity adjacent to the gate spacers. The second etch is highly selective to the spacer material, which prevents damage to the spacers during the exposure (opening) of the source/drain regions.

Abstract translation: 本发明的实施例提供了改进的接触和制造方法。 在包括栅极和源极/漏极区域的晶体管结构上形成介电层。 使用可以是反应离子蚀刻的第一蚀刻来部分地凹陷介电层。 然后使用第二蚀刻来继续蚀刻介电层以形成与栅极间隔物相邻的空腔。 第二蚀刻对间隔物材料具有高选择性，这防止了在源极/漏极区域的曝光（打开）期间损坏间隔物。