公开(公告)号：US20190013269A1

公开(公告)日：2019-01-10

申请号：US15643032

申请日：2017-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Chanro Park ,  Lei Sun ,  Yi Qi ,  Roderick Augur

IPC: H01L23/522 ,  H01L23/528 ,  H01L49/02 ,  H01L21/768 ,  H01L21/311 ,  H01L21/3213

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. A layer stack is deposited that includes a first conductor layer, a second conductor layer, and a third conductor layer. The layer stack is patterned to define a first electrode of the MIM capacitor from the first conductor layer, a second electrode of the MIM capacitor from the second conductor layer, and a third electrode of the MIM capacitor from the third conductor layer. A via opening is formed that extends vertically through the layer stack. The first electrode is recessed relative to the second electrode to define a cavity that is laterally offset from the via opening. A dielectric inner spacer is formed in the cavity. A conductive via is formed in the first via opening after the dielectric inner spacer is formed.

公开(公告)号：US10109526B1

公开(公告)日：2018-10-23

申请号：US15609408

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  J. Jay McMahon ,  Ryan S. Smith ,  Errol Todd Ryan ,  Shao Beng Law

IPC: H01L21/768

Abstract: Structures for a skip via and methods of forming a skip via in an interconnect structure. A metallization level is formed that includes a dielectric layer with a top surface. An opening is formed that extends vertically from the top surface of the dielectric layer into the dielectric layer. A dielectric cap layer is deposited on a bottom surface of the opening. A fill layer is formed inside the opening and extends from the top surface of the dielectric layer to the dielectric cap layer on the bottom surface of the opening. A via opening is etched that extends vertically through the fill layer to the dielectric cap layer on the bottom surface of the opening.

公开(公告)号：US20180261457A1

公开(公告)日：2018-09-13

申请号：US15457200

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao Beng Law ,  Xunyuan Zhang ,  Errol Todd Ryan ,  Nicholas LiCausi

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/28556 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32051 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

Abstract: Methods of forming non-mandrel cuts. A dielectric layer is formed on a metal hardmask layer, and a patterned sacrificial layer is formed on the dielectric layer. The dielectric layer is etched to form a non-mandrel cut in the dielectric layer that is vertically aligned with the opening in the patterned sacrificial layer. A metal layer is formed on an area of the metal hardmask layer exposed by the non-mandrel cut in the dielectric layer. The metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.

公开(公告)号：US10026687B1

公开(公告)日：2018-07-17

申请号：US15437100

申请日：2017-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean Xuan Lin ,  Xunyuan Zhang ,  Shao Beng Law ,  James Jay McMahon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/522 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.

公开(公告)号：US10014215B2

公开(公告)日：2018-07-03

申请号：US15689413

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre Labonte ,  Ruilong Xie ,  Xunyuan Zhang

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/532 ,  H01L23/535 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/823431 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a high-k dielectric liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the cap. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core and liner at an intermediate portion of the CB trench. The core is selectively etched relative to the liner to extend the CB trench to a bottom at the gate metal. The CB trench is metalized to form a CB contact.

公开(公告)号：US09941278B2

公开(公告)日：2018-04-10

申请号：US15202764

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andre Labonte ,  Ruilong Xie ,  Xunyuan Zhang

IPC: H01L23/522 ,  H01L27/088 ,  H01L29/66 ,  H01L29/45 ,  H01L21/311 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/8234 ,  H01L23/532 ,  H01L21/768 ,  H01L29/417

CPC classification number: H01L27/0886 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76889 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5226 ,  H01L23/53209 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method provides a structure having a FinFET in an Rx region, the FinFET including a channel, source/drain (S/D) regions and a gate, the gate including gate metal. A cap is formed over the gate having a liner and a core. Trench silicide (TS) is disposed on sides of the gate. The TS is recessed to a level above a level of the gate and below a level of the core. The liner is etched to the level of the TS. An oxide layer is disposed over the structure. A CB trench is patterned into the oxide layer within the Rx region to expose the core at a shelf portion of the CB trench. The core is etched to extend the CB trench to a bottom at the gate metal. The shelf portion having a larger area than the bottom. The CB trench is metalized to form a CB contact.

公开(公告)号：US09922929B1

公开(公告)日：2018-03-20

申请号：US15363513

申请日：2016-11-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Roderick A. Augur ,  Hoon Kim

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53257 ,  H01L21/7682 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self aligned interconnect structures and methods of manufacture. The structure includes an interconnect structure which is self-aligned with an upper level via metallization, and both the interconnect structure and the upper level via metallization are composed of a Pt group material.

公开(公告)号：US09805972B1

公开(公告)日：2017-10-31

申请号：US15437065

申请日：2017-02-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Sean Xuan Lin ,  James Jay McMahon ,  Shao Beng Law

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L21/768 ,  H01L21/288 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76816 ,  H01L21/288 ,  H01L21/76813 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/14 ,  H01L2924/15787

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; an upper wiring layer with one or more wiring structures, located above the first wiring layer; a blocking material which contacts at least one of the wiring structures of the upper wiring layer; a skip via with metallization, the skip via passes through the upper wiring layer and makes contact with the one or more wiring structures of the first wiring layer; and a conductive material in the skip via above the metallization and in a via interconnect above the blocking material.

公开(公告)号：US09799555B1

公开(公告)日：2017-10-24

申请号：US15175573

申请日：2016-06-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Frank W. Mont

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76849 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53266

Abstract: Interconnects for a chip and methods of forming such interconnects. An opening is formed in a dielectric layer and a contact is formed in the opening. A metal cap is formed on a top surface of the contact. The contact is comprised of cobalt, and the metal cap covers the top surface of the contact.

公开(公告)号：US20170125530A1

公开(公告)日：2017-05-04

申请号：US14927765

申请日：2015-10-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Ruilong Xie ,  Sean X. Lin

IPC: H01L29/417 ,  H01L21/288 ,  H01L29/45 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66

CPC classification number: H01L29/41791 ,  H01L21/288 ,  H01L29/401 ,  H01L29/41766 ,  H01L29/42372 ,  H01L29/456 ,  H01L29/495 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: One illustrative method disclosed includes, among other things, forming a gate contact opening in a layer of insulating material, performing at least one etching process through the gate contact opening to remove a gate cap layer and to expose the gate structure, selectively growing a metal material that is conductively coupled to an upper surface of the gate structure such that the grown metal material contacts all of the sidewalls of the gate contact opening and an air space is formed between a bottom of the grown metal material and a conductive source/drain structure, and forming one or more conductive materials in the gate contact opening above the grown metal material.