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    Transistors and memory arrays
    124.
    发明授权
    Transistors and memory arrays 有权

    公开(公告)号：US11605723B2

    公开(公告)日：2023-03-14

    申请号：US16940746

    申请日：2020-07-28

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Sills ,  Durai Vishak Nirmal Ramaswamy

    IPC: H01L21/00 ,  H01L29/51 ,  H01L27/11507 ,  H01L27/108 ,  H01L27/11504 ,  H01L29/78 ,  H01L29/40 ,  H01L27/11514 ,  H01L29/24 ,  H01L27/11509

    Abstract: Some embodiments include integrated memory having an array of access transistors. Each access transistor includes an active region which has a first source/drain region, a second source/drain region and a channel region. The active regions of the access transistors include semiconductor material having elements selected from Groups 13 and 16 of the periodic table. First conductive structures extend along rows of the array and have gating segments adjacent the channel regions of the access transistors. Heterogenous insulative regions are between the gating segments and the channel regions. Second conductive structures extend along columns of the array, and are electrically coupled with the first source/drain regions. Storage-elements are electrically coupled with the second source/drain regions. Some embodiments include a transistor having a semiconductor oxide channel material. A conductive gate material is adjacent to the channel material. A heterogenous insulative region is between the gate material and the channel material.

    Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors
    125.
    发明申请
    Array Of Vertical Transistors And Method Used In Forming An Array Of Vertical Transistors 有权

    公开(公告)号：US20230014320A1

    公开(公告)日：2023-01-19

    申请号：US17947401

    申请日：2022-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

    IPC: H01L27/12 ,  H01L21/84

    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

    Array of vertical transistors and method used in forming an array of vertical transistors
    127.
    发明授权
    Array of vertical transistors and method used in forming an array of vertical transistors 有权

    公开(公告)号：US11488981B2

    公开(公告)日：2022-11-01

    申请号：US16934607

    申请日：2020-07-21

    Applicant: Micron Technology, Inc.

    Inventor： Yi Fang Lee ,  Jaydip Guha ,  Lars P. Heineck ,  Kamal M. Karda ,  Si-Woo Lee ,  Terrence B. McDaniel ,  Scott E. Sills ,  Kevin J. Torek ,  Sheng-Wei Yang

    IPC: H01L27/12 ,  H01L21/84 ,  H01L27/13

    Abstract: An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.

    Integrated Assemblies and Methods of Forming Integrated Assemblies
    130.
    发明申请
    Integrated Assemblies and Methods of Forming Integrated Assemblies 有权

    公开(公告)号：US20220109008A1

    公开(公告)日：2022-04-07

    申请号：US17061852

    申请日：2020-10-02

    Applicant: Micron Technology, Inc.

    Inventor： Scott E. Sills ,  Yi Fang Lee ,  Kevin J. Torek

    IPC: H01L27/12

    Abstract: Some embodiments include an integrated assembly which includes a base structure. The base structure includes a series of conductive structures which extend along a first direction. The conductive structures have steps which alternate with recessed regions along the first direction. Pillars of semiconductor material are over the steps. The semiconductor material includes at least one element selected from Group 13 of the periodic table in combination with at least one element selected from Group 16 of the periodic table. The semiconductor material may be semiconductor oxide in some applications. Some embodiments include methods of forming integrated assemblies.

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