公开(公告)号：US20180040627A1

公开(公告)日：2018-02-08

申请号：US15231205

申请日：2016-08-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Senaka Kanakamedala ,  Rahul Sharangpani ,  Raghuveer S. Makala ,  Somesh Peri ,  Yao-Sheng Lee

IPC: H01L27/115 ,  H01L23/528

CPC classification number: H01L27/11582 ,  H01L23/5283 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575

Abstract: After formation of a memory opening through an alternating stack of insulating layers and sacrificial material layers, a blocking dielectric having a greater thickness at levels of the insulating layers than at levels of the sacrificial material layers is formed around, or within, the memory opening. A memory stack structure is formed within the memory opening. Backside recesses are formed by removing the sacrificial material layers and surface portions of the blocking dielectric to form backside recesses including vertically expanded end portions. Electrically conductive layers are formed within the backside recesses. Each of the electrically conductive layers is a control gate electrode which includes a uniform thickness portion and a ridged end portion having a greater vertical extent than the uniform thickness region. The ridged end portion laterally surrounds the memory stack structure and provides a longer gate length for the control gate electrodes for the memory stack structure.

公开(公告)号：US09812463B2

公开(公告)日：2017-11-07

申请号：US15250185

申请日：2016-08-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Senaka Kanakamedala ,  Fei Zhou ,  Somesh Peri ,  Masanori Tsutsumi ,  Keerti Shukla ,  Yusuke Ikawa ,  Kiyohiko Sakakibara ,  Eisuke Takii

IPC: H01L21/00 ,  H01L27/11582 ,  H01L29/51 ,  H01L21/02 ,  H01L27/11573

CPC classification number: H01L27/11582 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02247 ,  H01L21/02326 ,  H01L21/31111 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A memory opening can be formed through an alternating stack of insulating layers and sacrificial material layers provided over a substrate. Annular etch stop material portions are provided at each level of the sacrificial material layers around the memory opening. The annular etch stop material portions can be formed by conversion of surface portions of the sacrificial material layers into dielectric material portion, or by recessing the sacrificial material layers around the memory opening and filling indentations around the memory opening. After formation of a memory stack structure, the sacrificial material layers are removed from the backside. The annular etch stop material portions are at least partially converted to form charge trapping material portions. Vertical isolation of the charge trapping material portions among one another around the memory stack structure minimizes leakage between the charge trapping material portions located at different word line levels.

公开(公告)号：US20170162597A1

公开(公告)日：2017-06-08

申请号：US15440365

申请日：2017-02-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Sateesh Koka ,  Raghuveer S. Makala ,  Srikanth Ranganathan ,  Mark Juanitas ,  Johann Alsmeier

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11529 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11524

CPC classification number: H01L27/11582 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/02299 ,  H01L21/02321 ,  H01L21/02356 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31155 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/7883

Abstract: A method of manufacturing a semiconductor structure includes forming a stack of alternating layers comprising insulating layers and spacer material layers over a semiconductor substrate, forming a memory opening through the stack, forming an aluminum oxide layer having a horizontal portion at a bottom of the memory opening and a vertical portion at least over a sidewall of the memory opening, where the horizontal portion differs from the vertical portion by at least one of structure or composition, and selectively etching the horizontal portion selective to the vertical portion.

公开(公告)号：US09646990B2

公开(公告)日：2017-05-09

申请号：US15179318

申请日：2016-06-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Sateesh Koka ,  Raghuveer S. Makala ,  Yanli Zhang ,  Senaka Kanakamedala ,  Rahul Sharangpani ,  Yao-Sheng Lee ,  George Matamis

IPC: H01L29/78 ,  H01L29/788 ,  H01L21/336 ,  H01L29/792 ,  H01L21/311 ,  H01L27/11582 ,  H01L29/66 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/66666 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.

公开(公告)号：US12243776B2

公开(公告)日：2025-03-04

申请号：US17508036

申请日：2021-10-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Roshan Jayakhar Tirukkonda ,  Senaka Kanakamedala ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Monica Titus ,  Adarsh Rajashekhar

IPC: H01L21/768 ,  H01L21/306 ,  H01L21/308

Abstract: A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.

公开(公告)号：US12219776B2

公开(公告)日：2025-02-04

申请号：US17578199

申请日：2022-01-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Kartik Sondhi

IPC: H10B51/20 ,  H01L23/48 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.

公开(公告)号：US12087628B2

公开(公告)日：2024-09-10

申请号：US17566262

申请日：2021-12-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fumitaka Amano

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/535

CPC classification number: H01L21/76895 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/535

Abstract: A semiconductor structure includes a first dielectric material layer, a first metal interconnect structure embedded within the first dielectric material layer and including a first metallic material portion including a first metal, a second dielectric material layer located over the first dielectric material layer, and a second metal interconnect structure embedded within the second dielectric material layer and including an integrated line-and-via structure that includes a second metallic material portion including a second metal. A metal-semiconductor alloy portion including a first metal-semiconductor alloy of the first metal and a semiconductor material is located underneath the second metallic material portion, and contacts a top surface of the first metal interconnect structure.

公开(公告)号：US11990413B2

公开(公告)日：2024-05-21

申请号：US17399710

申请日：2021-08-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Linghan Chen ,  Raghuveer S. Makala ,  Fumitaka Amano

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/53219 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/53223 ,  H10B41/27 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. The electrically conductive layers include an intermetallic alloy of aluminum and at least one metal other than aluminum. Memory openings vertically extend through the alternating stack. Memory opening fill structures are located in a respective one of the memory openings and include a respective vertical semiconductor channel and a respective vertical stack of memory elements.

公开(公告)号：US11968834B2

公开(公告)日：2024-04-23

申请号：US17192463

申请日：2021-03-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Raghuveer S. Makala ,  Senaka Kanakamedala ,  Fei Zhou

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack and having lateral protrusions at levels of the electrically conductive layers, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner and located within volumes of the lateral protrusions. Each discrete memory element includes a vertical inner sidewall and a convex or stepped outer sidewall.

公开(公告)号：US11968826B2

公开(公告)日：2024-04-23

申请号：US17244186

申请日：2021-04-29

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Raghuveer S. Makala ,  Senaka Kanakamedala ,  Rahul Sharangpani

IPC: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings extending through the alternating stack, and memory opening fill structures located in the memory openings and containing a respective vertical semiconductor channel and a respective memory film. Each of the electrically conductive layers includes a tubular metallic liner in contact with a respective outer sidewall segment of a respective one of the memory opening fill structures, an electrically conductive barrier layer contacting the respective tubular metallic liner and two of the insulating layers, and a metallic fill material layer contacting the electrically conductive barrier layer, and not contacting the tubular metallic liner or any of the insulating layers. The memory opening fill structures are formed after performing a halogen outgassing anneal through the memory openings to reduce or eliminate the halogen outgassing damage in the layers of the memory film.