公开(公告)号：US20150255165A1

公开(公告)日：2015-09-10

申请号：US14196839

申请日：2014-03-04

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Hung Quoc Nguyen ,  Anh Ly ,  Thuan Vu

IPC: G11C16/28

CPC classification number: G11C16/28 ,  G11C7/065 ,  G11C11/1673 ,  G11C13/004 ,  G11C16/0425 ,  G11C2216/04

Abstract: Improved sensing circuits for use in low power nanometer flash memory devices are disclosed.

Abstract translation: 公开了用于低功率纳米闪速存储器件的改进的感测电路。

公开(公告)号：US09123401B2

公开(公告)日：2015-09-01

申请号：US13652447

申请日：2012-10-15

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C5/14 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C8/08

CPC classification number: G11C5/145 ,  G11C8/08 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/10

Abstract: A non-volatile memory device that includes N planes of non-volatile memory cells (where N is an integer greater than 1). Each plane of non-volatile memory cells includes a plurality of memory cells configured in rows and columns. Each of the N planes includes gate lines that extend across the rows of the memory cells therein but do not extend to others of the N planes of non-volatile memory cells. A controller is configured to divide each of a plurality of words of data into N fractional-words, and program each of the N fractional-words of each word of data into a different one of the N planes of non-volatile memory cells. The controller uses a programming current and a program time period for the programming, and can be configured to vary the programming current by a factor and inversely vary the program time period by the factor.

Abstract translation: 包括非易失性存储器单元的N个平面（其中N是大于1的整数）的非易失性存储器件。 非易失性存储单元的每个平面包括以行和列配置的多个存储器单元。 N平面中的每一个包括在其中存储单元的行延伸但不延伸到非易失性存储单元的N个平面中的其他平面的栅极线。 控制器被配置为将多个数据字中的每一个分成N个小数字，并且将每个数据字的N个分数字中的每一个分解成非易失性存储单元的N个平面中的不同的一个。 控制器使用编程电流和编程时间段进行编程，并且可以配置为通过一个因素改变编程电流，并根据因子反向改变程序时间段。

公开(公告)号：US20140269061A1

公开(公告)日：2014-09-18

申请号：US13958415

申请日：2013-08-02

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen ,  Vipin Tiwari

IPC: G11C16/28 ,  G11C16/06

CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C7/067 ,  G11C7/12 ,  G11C16/00 ,  G11C16/06 ,  G11C16/24 ,  G11C16/26 ,  G11C2207/063 ,  H01L27/11519

Abstract: Improved sensing circuits and improved bit line layouts for advanced nanometer flash memory devices are disclosed.

Abstract translation: 公开了用于高级纳米闪存器件的改进的感测电路和改进的位线布局。

公开(公告)号：US20140264539A1

公开(公告)日：2014-09-18

申请号：US14191625

申请日：2014-02-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Hieu Van Tran ,  Chien-Sheng Su ,  Prateep Tuntasood

IPC: H01L27/115

CPC classification number: H01L21/76224 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7881

Abstract: A memory device array with spaced apart parallel isolation regions formed in a semiconductor substrate, with an active region between each pair of adjacent isolation regions. Each isolation region includes a trench formed into the substrate surface and an insulation material formed in the trench. Portions of a top surface of the insulation material are recessed below the surface of the substrate. Each active region includes a column of memory cells each having spaced apart first and second regions with a channel region therebetween, a floating gate over a first channel region portion, and a select gate over a second channel region portion. The select gates are formed as continuous word lines extending perpendicular to the isolation regions and each forming the select gates for one row of the memory cells. Portions of each word line extend down into the trenches and disposed laterally adjacent to sidewalls of the trenches.

Abstract translation: 一种存储器件阵列，其具有形成在半导体衬底中的间隔开的平行隔离区域，在每对相邻隔离区域之间具有有源区域。 每个隔离区域包括形成在衬底表面中的沟槽和形成在沟槽中的绝缘材料。 绝缘材料的顶表面的部分凹陷在基底的表面下方。 每个有源区域包括一列存储单元，每个存储单元具有间隔开的第一和第二区域，其间具有通道区域，在第一沟道区域部分上的浮动栅极以及在第二沟道区域部分上的选择栅极。 选择栅极形成为垂直于隔离区域延伸的连续字线，并且每个形成用于一行存储器单元的选择栅极。 每个字线的一部分向下延伸到沟槽中并且横向设置成与沟槽的侧壁相邻。

公开(公告)号：US20250167799A1

公开(公告)日：2025-05-22

申请号：US18426071

申请日：2024-01-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Andrew Kunil Choe ,  Hoa Vu

IPC: H03M3/00 ,  G06F17/16 ,  H03M1/46

Abstract: In one example, a system comprises a vector-by-matrix multiplication array comprising an array of non-volatile memory cells arranged in rows and columns; and a sigma-delta analog-to-digital converter to receive a current from a column of the vector-by-matrix multiplication array and to generate a digital output in response to the current.

公开(公告)号：US12237011B2

公开(公告)日：2025-02-25

申请号：US17853315

申请日：2022-06-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Han Tran ,  Kha Nguyen ,  Hien Pham

IPC: G11C11/56 ,  G06F17/16 ,  G06N3/06 ,  G11C11/16 ,  G11C11/4074

Abstract: Various examples of decoders and physical layout designs for non-volatile flash memory arrays in an analog neural system are disclosed. In one example, a system comprises a plurality of vector-by-matrix multiplication arrays in an analog neural memory system, each vector-by-matrix multiplication array comprising an array of non-volatile memory cells organized into rows and columns, wherein each memory cell comprises a word line terminal; a plurality of read row decoders, each read row decoder coupled to one of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows during a read operation; and a shared program row decoder coupled to all of the plurality of vector-by-matrix multiplication arrays for applying a voltage to one or more selected rows in one or more of the vector-by-matrix multiplication arrays during a program operation.

公开(公告)号：US12230319B2

公开(公告)日：2025-02-18

申请号：US17585452

申请日：2022-01-26

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G11C11/54 ,  G06N3/063 ,  G11C16/04 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  H10B41/30

Abstract: Numerous embodiments for improving an analog neural memory in a deep learning artificial neural network as to accuracy or power consumption as temperature changes are disclosed. In some embodiments, a method is performed to determine in real-time a bias value to apply to one or more memory cells in a neural network. In other embodiments, a bias voltage is determined from a lookup table and is applied to a terminal of a memory cell during a read operation.

公开(公告)号：US12198043B2

公开(公告)日：2025-01-14

申请号：US18522153

申请日：2023-11-28

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten ,  Nhan Do

IPC: G06N3/065 ,  G06F3/06 ,  G06F17/16 ,  G06N3/08 ,  G11C27/02

Abstract: In one example, a circuit comprises an input transistor comprising a first terminal, a second terminal coupled to ground, and a gate; a capacitor comprising a first terminal and a second terminal; an output transistor comprising a first terminal providing an output current, a second terminal coupled to ground, and a gate; a first switch; and a second switch; wherein in a first mode, the first switch is closed and couples an input current to the first terminal of the input transistor and the gate of the input transistor and the second switch is closed and couples the first terminal of the input transistor to the first terminal of the capacitor and the gate of the output transistor, and in a second mode, the first switch is open and the second switch is open and the capacitor discharges into the gate of the output transistor.

公开(公告)号：US12131786B2

公开(公告)日：2024-10-29

申请号：US18104228

申请日：2023-01-31

Applicant: Silicon Storage Technology, Inc.

Inventor： Louisa Schneider ,  Xian Liu ,  Steven Lemke ,  Parviz Ghazavi ,  Jinho Kim ,  Henry A. Om'Mani ,  Hieu Van Tran ,  Nhan Do

IPC: G11C5/06 ,  G11C16/16 ,  H01L23/48 ,  H01L29/423 ,  H10B41/10 ,  H10B41/27

CPC classification number: G11C16/16 ,  H01L23/481 ,  H01L29/42328 ,  H10B41/10 ,  H10B41/27

Abstract: A memory cell array having rows and columns of memory cells with respective ones of the memory cells including spaced apart source and drain regions formed in a semiconductor substrate with a channel region extending there between, a floating gate over a first portion of the channel region, a select gate over a second portion of the channel region, and an erase gate over the source region. A strap region is disposed between first and second pluralities of the columns. For one memory cell row, a dummy floating gate is disposed in the strap region, an erase gate line electrically connects together the erase gates of the memory cells in the one row and in the first plurality of columns, wherein the erase gate line is aligned with the dummy floating gate with a row direction gap between the erase gate line and the dummy floating gate.

公开(公告)号：US20240338177A1

公开(公告)日：2024-10-10

申请号：US18218368

申请日：2023-07-05

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran

IPC: G06F7/523 ,  G06F7/501 ,  G06F17/16 ,  G11C11/54

CPC classification number: G06F7/523 ,  G06F7/501 ,  G06F17/16 ,  G11C11/54

Abstract: In one example disclosed herein, a system comprises an analog computation-in-memory engine to perform operations in a first layer in a neural network and a digital computation-in-memory engine to perform operations in a second layer different than the first layer in the neural network. The system optionally comprises a dynamic weight engine to perform operations in a third layer different than the first layer and the second layer in the neural network.