公开(公告)号：US20230268346A1

公开(公告)日：2023-08-24

申请号：US17700475

申请日：2022-03-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chin-Hung Chen

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/8238

CPC classification number: H01L27/0922 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/31053 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0924

Abstract: A method for fabricating a semiconductor device includes the steps of: providing a substrate having a high-voltage (HV) region and a low-voltage (LV) region; forming a base on the HV region and fin-shaped structures on the LV region; forming a first insulating around the fin-shaped structures; removing the base, the first insulating layer, and part of the fin-shaped structures to form a first trench in the HV region and a second trench in the LV region; forming a second insulating layer in the first trench and the second trench; and planarizing the second insulating layer to form a first shallow trench isolation (STI) on the HV region and a second STI on the LV region.

公开(公告)号：US20230215855A1

公开(公告)日：2023-07-06

申请号：US17673749

申请日：2022-02-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Yu-Hsiang Lin ,  Ssu-I Fu ,  Chih-Kai Hsu

IPC: H01L25/18 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  H01L25/50 ,  H01L25/0657 ,  H01L24/08

Abstract: A method for fabricating semiconductor device includes the steps of first providing a first substrate having a high-voltage (HV) region and a medium voltage (MV) region and a second substrate having a low-voltage (LV) region and a static random access memory (SRAM) region, in which the HV region includes a HV device, the MV region includes a MV device, the LV region includes a fin field-effect transistor (FinFET), and the SRAM region includes a SRAM device. Next, a bonding process is conducted by using hybrid bonding, through-silicon interposer (TSI) or redistribution layer (RDL) for bonding the first substrate and the second substrate.

公开(公告)号：US20230197710A1

公开(公告)日：2023-06-22

申请号：US17585582

申请日：2022-01-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Kai Hsu ,  Ssu-I Fu ,  Yu-Hsiang Lin ,  Chien-Ting Lin ,  Chia-Jung Hsu ,  Chun-Ya Chiu ,  Chin-Hung Chen

IPC: H01L27/02 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L27/0266 ,  H01L29/41791 ,  H01L29/7851 ,  H01L29/66795 ,  H01L29/0653

Abstract: A method for fabricating a semiconductor device includes first providing a substrate having a high-voltage (HV) region, a medium-voltage (MV) region, and a low-voltage (LV) region, forming a HV device on the HV region, and forming a LV device on the LV region. Preferably, the HV device includes a first base on the substrate, a first gate dielectric layer on the first base, and a first gate electrode on the first gate dielectric layer. The LV device includes a fin-shaped structure on the substrate, and a second gate electrode on the fin-shaped structure, in which a top surface of the first gate dielectric layer is lower than a top surface of the fin-shaped structure.

公开(公告)号：US20230084241A1

公开(公告)日：2023-03-16

申请号：US17500971

申请日：2021-10-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Chien-Ting Lin

IPC: H01L43/14 ,  H01L27/22 ,  H01L43/04 ,  H01L43/06

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) stack on a substrate, forming an etch stop layer on the MTJ stack, forming a first spin orbit torque (SOT) layer on the etch stop layer, and then patterning the first SOT layer, the etch stop layer, and the MTJ stack to form a MTJ.

公开(公告)号：US20210035620A1

公开(公告)日：2021-02-04

申请号：US16556170

申请日：2019-08-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yu-Ping Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Yi-Hui Lee ,  Ying-Cheng Liu ,  Yi-An Shih ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Chien-Ting Lin

IPC: G11C11/16 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L27/22

Abstract: A method for forming a semiconductor structure is disclosed. A substrate having a logic device region and a memory device region is provided. A first dielectric layer is formed on the substrate. Plural memory stack structures are formed on the first dielectric layer on the memory device region. An insulating layer is formed and conformally covers the memory stack structures and the first dielectric layer. An etching back process is performed to remove a portion of the insulating layer without exposing any portion of the memory stack structures. After the etching back process, a second dielectric layer is formed on the insulating layer and completely fills the spaces between the memory stack structures.

公开(公告)号：US09825144B2

公开(公告)日：2017-11-21

申请号：US15644850

申请日：2017-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/76 ,  H01L29/49 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

公开(公告)号：US20170309722A1

公开(公告)日：2017-10-26

申请号：US15644850

申请日：2017-07-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Fang Tzou ,  Chien-Ming Lai ,  Yi-Wen Chen ,  Hung-Yi Wu ,  Tong-Jyun Huang ,  Chien-Ting Lin ,  Chun-Hsien Lin

IPC: H01L29/49 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/4966 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/42364 ,  H01L29/66545

Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

公开(公告)号：US20170178972A1

公开(公告)日：2017-06-22

申请号：US15447126

申请日：2017-03-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/66803

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

公开(公告)号：US09627268B2

公开(公告)日：2017-04-18

申请号：US14884746

申请日：2015-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Yu Chang ,  Li-Wei Feng ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin ,  Yi-Ren Chen ,  Shou-Wei Hsieh ,  Hsin-Yu Chen ,  Chun-Hao Lin

IPC: H01L21/8238 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/02129 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a fin-shaped structure thereon and a shallow trench isolation (STI) around the fin-shaped structure, in which the fin-shaped structure has a top portion and a bottom portion; forming a first doped layer on the STI and the top portion; and performing a first anneal process.

公开(公告)号：US20170103981A1

公开(公告)日：2017-04-13

申请号：US14880284

申请日：2015-10-12

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chih-Kai Hsu ,  Jyh-Shyang Jenq ,  Chien-Ting Lin

IPC: H01L27/07 ,  H01L29/06 ,  H01L21/283 ,  H01L21/768 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/0649 ,  H01L21/283 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0629 ,  H01L28/00 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a first fin-shaped structure on a first region and a second fin-shaped structure on a second region; forming a plurality of first gate structures on the first fin-shaped structure, a plurality of second gate structures on the second fin-shaped structure, and an interlayer dielectric (ILD) layer around the first gate structures and the second gate structures; forming a patterned mask on the ILD layer; and using the patterned mask to remove all of the ILD layer from the first region and part of the ILD layer from the second region for forming a plurality of first contact holes in the first region and a plurality of second contact holes in the second region.