公开(公告)号：US09331202B2

公开(公告)日：2016-05-03

申请号：US14731876

申请日：2015-06-05

申请人： GLOBALFOUNDRIES Inc.

发明人： Bingwu Liu ,  Hui Zang

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/84 ,  H01L29/423 ,  H01L21/8234

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818

摘要： One illustrative method disclosed herein includes, among other things, forming a fin protection layer around a fin, forming a sacrificial gate electrode above a section of the fin protection layer, forming at least one sidewall spacer adjacent the sacrificial gate electrode, removing the sacrificial gate electrode to define a gate cavity that exposes a portion of the fin protection layer, oxidizing at least the exposed portion of the fin protection layer to thereby form an oxidized portion of the fin protection layer, and removing the oxidized portion of the fin protection layer so as to thereby expose a surface of the fin within the gate cavity.

摘要翻译： 本文公开的一种说明性方法包括在鳍周围形成翅片保护层，在翅片保护层的一部分上形成牺牲栅电极，形成邻近牺牲栅电极的至少一个侧壁间隔物，去除牺牲栅极 电极，以限定露出所述鳍片保护层的一部分的栅极腔，至少氧化所述鳍片保护层的暴露部分，从而形成所述鳍片保护层的氧化部分，以及去除所述鳍片保护层的氧化部分，从而 从而使得在门腔内的翅片的表面露出。

公开(公告)号：US09331079B2

公开(公告)日：2016-05-03

申请号：US14694355

申请日：2015-04-23

申请人： Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Qiuhua Han

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/265 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/3105 ,  H01L21/762

CPC分类号： H01L27/0924 ,  H01L21/265 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31055 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76224 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a plurality of fins on the semiconductor substrate, forming a plurality of shallow trench isolation (STI) structures on the semiconductor substrate on opposite sides of the fins, forming a dummy gate on the fins, forming gate spacers on opposite sides of the dummy gate, etching a first portion of the STI structures disposed outside a gate region, the first portion having a first predetermined thickness, forming an interlayer dielectric over the semiconductor substrate, removing the dummy gate, etching a second portion of the STI structures disposed in the gate region, the second portion having a second predetermined thickness, and forming a high-k dielectric layer and a metal gate in an area where the dummy gate is removed.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括提供半导体衬底，在半导体衬底上形成多个散热片，在散热片的相对侧上的半导体衬底上形成多个浅沟槽隔离（STI）结构，在翅片上形成虚拟栅极，形成栅极 在伪栅极的相对侧上的间隔物，蚀刻设置在栅极区域外部的STI结构的第一部分，第一部分具有第一预定厚度，在半导体衬底上形成层间电介质，去除虚拟栅极，蚀刻第二部分 设置在栅极区域中的STI结构，第二部分具有第二预定厚度，并且在去除虚拟栅极的区域中形成高k电介质层和金属栅极。

公开(公告)号：US20160118462A1

公开(公告)日：2016-04-28

申请号：US14987351

申请日：2016-01-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hsiang-Jen Tseng ,  Ting-Wei Chiang ,  Wei-Yu Chen ,  Kuo-Nan Yang ,  Ming-Hsiang Song ,  Ta-Pen Guo

IPC分类号： H01L29/08 ,  H01L21/306 ,  H01L29/78 ,  H01L21/283 ,  H01L29/417 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234

CPC分类号： H01L29/0847 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823814 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/41758 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7835 ,  H01L29/785

摘要： Embodiments of the present disclosure are a semiconductor device, a FinFET device, and a method of forming a FinFET device. An embodiment is a semiconductor device comprising a first semiconductor fin extending above a substrate, a first source region on the first semiconductor fin, and a first drain region on the first semiconductor fin. The first source region has a first width and the first drain region has a second width with the second width being different than the first width.

摘要翻译： 本公开的实施例是半导体器件，FinFET器件和形成FinFET器件的方法。 实施例是一种半导体器件，包括在衬底上延伸的第一半导体鳍片，第一半导体鳍片上的第一源极区域和第一半导体鳍片上的第一漏极区域。 第一源区具有第一宽度，第一漏区具有第二宽度，第二宽度不同于第一宽度。

公开(公告)号：US20160111340A1

公开(公告)日：2016-04-21

申请号：US14984231

申请日：2015-12-30

申请人： International Business Machines Corporation

发明人： Pranita Kerber ,  Qiqing C. Ouyang ,  Alexander Reznicek

IPC分类号： H01L21/8238 ,  H01L21/02

CPC分类号： H01L21/823821 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66 ,  H01L29/6681

摘要： A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel.

公开(公告)号：US20160111320A1

公开(公告)日：2016-04-21

申请号：US14515628

申请日：2014-10-16

申请人： GLOBALFOUNDRIES Inc.

发明人： Hongliang SHEN ,  Zhenyu HU ,  Jin Ping LIU

IPC分类号： H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311 ,  H01L27/088 ,  H01L29/06

CPC分类号： H01L21/76232 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/6681

摘要： Semiconductor devices and fabrication methods are provided having an isolation feature within a fin structure which, for instance, facilitates isolating circuit elements supported by the fin structure. The fabrication method includes, for instance, providing an isolation material disposed, in part, within the fin structure, the isolation material being formed to include a T-shaped isolation region and a first portion extending into the fin structure, and a second portion disposed over the first portion and extending above the fin structure.

摘要翻译： 提供半导体器件和制造方法，其具有翅片结构内的隔离特征，其例如有助于隔离由鳍结构支撑的电路元件。 制造方法包括例如提供部分地设置在鳍结构内的隔离材料，隔离材料被形成为包括T形隔离区域和延伸到翅片结构中的第一部分，并且第二部分设置在 在第一部分之上并且延伸到翅片结构之上。

公开(公告)号：US09318582B2

公开(公告)日：2016-04-19

申请号：US14215564

申请日：2014-03-17

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz ,  Sreenivasan Raghavasimhan

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823468 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785 ,  H01L29/7856

摘要： After forming a gate spacer on each sidewall of a sacrificial gate structure, portions of each dielectric fin cap portion underneath the gate spacer is intentionally etched and undercut regions that are formed are filled and pinched off with a dielectric material of a conformal dielectric liner. Portions of the conformal dielectric liner in the undercut regions are not subject to the undercut during an epitaxial pre-clean process performed prior to forming an epitaxial source region and an epitaxial drain region on opposite sides of the sacrificial gate structure and remain in the undercut regions after forming the epitaxial source region and the epitaxial drain region.

摘要翻译： 在牺牲栅极结构的每个侧壁上形成栅极间隔物之后，有意地蚀刻在栅极间隔物下面的每个介电鳍帽部分的部分，并且用形成的绝缘电介质衬垫的电介质材料填充并夹住形成的底切区域。 在形成外延源区域和在牺牲栅极结构的相对侧上的外延漏极区域之后执行的外延预清洁工艺期间，底切区域中的共形绝缘衬垫的部分不会受到底切，并且保留在底切区域 在形成外延源极区域和外延漏极区域之后。

公开(公告)号：US09312367B2

公开(公告)日：2016-04-12

申请号：US14511884

申请日：2014-10-10

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz

IPC分类号： H01L29/66 ,  H01L21/02

CPC分类号： H01L29/161 ,  H01L21/02381 ,  H01L21/02532 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/7851

摘要： A gate cavity is formed exposing a portion of a silicon fin by removing a sacrificial gate structure that straddles the silicon fin. An epitaxial silicon germanium alloy layer is formed within the gate cavity and on the exposed portion of the silicon fin. Thermal mixing or thermal condensation is performed to convert the exposed portion of the silicon fin into a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions. A functional gate structure is formed within the gate cavity providing a finFET structure having a silicon germanium alloy channel portion which is laterally surrounded by silicon fin portions.

摘要翻译： 通过去除横跨硅片的牺牲栅极结构，形成露出硅片的一部分的栅极腔。 外延硅锗合金层形成在栅极腔内和硅片的暴露部分上。 执行热混合或热凝结以将硅片的暴露部分转换成由硅片部分横向包围的硅锗合金通道部分。 在栅极腔内形成功能栅极结构，提供具有由硅片部分横向包围的硅锗合金沟道部分的finFET结构。

公开(公告)号：US20160093727A1

公开(公告)日：2016-03-31

申请号：US14963277

申请日：2015-12-09

申请人： International Business Machines Corporation

发明人： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Ali Khakifirooz ,  Charles W. Koburger, III

IPC分类号： H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A structure including a plurality of fins etched from a semiconductor substrate, a gate electrode above and perpendicular to the plurality of fins, a pair of sidewall spacers disposed on opposing sides of the gate electrode, a gap fill material above the semiconductor substrate and between the plurality of fins, the gap fill material is directly below the gate electrode and directly below the pair of sidewall spacers, wherein the gate electrode separates the gap fill material from each of the plurality of fins, and an epitaxially grown region above a portion of the plurality of fins not covered by the gate electrode, the EPI region separates the gap fill material from each of the plurality of fins.

摘要翻译： 包括从半导体衬底蚀刻的多个鳍片的结构，在多个鳍片上方并垂直于多个鳍片的栅极电极，设置在栅电极的相对侧上的一对侧壁间隔物，位于半导体衬底上方之间的间隙填充材料 多个翅片，间隙填充材料直接在栅电极下方并且直接在一对侧壁间隔件的下方，其中栅极电极将间隙填充材料与多个翅片中的每一个分开，并且在该部分上方的外延生长区域 多个翅片未被栅电极覆盖，EPI区域将间隙填充材料与多个翅片中的每一个分开。

公开(公告)号：US09299780B2

公开(公告)日：2016-03-29

申请号：US14225769

申请日：2014-03-26

申请人： International Business Machines Corporation

发明人： Brian J. Greene ,  Arvind Kumar ,  Dan M. Mocuta

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/16 ,  H01L29/165

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/785

摘要： A method of fabricating a semiconductor device includes forming a plurality of semiconductor fins on an insulator layer of a semiconductor substrate, and forming a plurality of gate stacks on the insulator layer. Each gate stack wraps around a respective portion of the semiconductor fins. The method further includes forming a dielectric layer on the insulator layer. The dielectric layer fills voids between the semiconductor fins and gate stacks, and covers the semiconductor fins. The method further includes etching at least one portion of the semiconductor fins until reaching the insulator layer such that at least one cavity is formed. The cavity exposes seed regions of the semiconductor fins located between adjacent gate stacks. The method further includes epitaxially growing a semiconductor material from the seed regions to form source/drain regions corresponding to a respective gate stack.

公开(公告)号：US09293583B2

公开(公告)日：2016-03-22

申请号：US14802110

申请日：2015-07-17

申请人： International Business Machines Corporation

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Kern Rim

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC分类号： H01L29/7849 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02238 ,  H01L21/76205 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

摘要： A method for inducing stress within the channel of a semiconductor fin structure includes forming a semiconductor fin on a substrate; forming a fin hard mask layer, multiple isolation regions, and multiple spacers, on the semiconductor fin; forming a gate structure on the semiconductor fin; and oxidizing multiple outer regions of the semiconductor fin to create oxidized stressors that induce compressive stress within the channel of the semiconductor fin. A method for inducing tensile stress within the channel of a semiconductor fin by oxidizing a central region of the semiconductor fin is also provided. Structures corresponding to the methods are also provided.

摘要翻译： 一种用于在半导体鳍片结构的沟道内引发应力的方法包括在衬底上形成半导体鳍片; 在半导体翅片上形成翅片硬掩模层，多个隔离区域和多个间隔物; 在半导体鳍片上形成栅极结构; 以及氧化半导体鳍片的多个外部区域以产生在半导体鳍片的沟道内引起压应力的氧化应激物。 还提供了通过氧化半导体鳍片的中心区域来在半导体鳍片的沟道内引起拉伸应力的方法。 还提供了与方法对应的结构。