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公开(公告)号：US12119908B2
公开(公告)日：2024-10-15
申请号：US17417637
申请日：2020-02-12
IPC分类号： H04B7/06 , H04B7/0456 , H04B7/08 , H04B17/318 , H04B17/336 , H04W16/28
CPC分类号： H04B7/0617 , H04B7/0456 , H04B7/0695 , H04B7/0857 , H04B7/088 , H04B17/318 , H04B17/336 , H04W16/28
摘要： A pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). Methods and systems for adapting beamwidth of beams on NR physical channels are provided. Alignment between beams of a UE and a gNB is created by refining beam codebooks. Phase shifters and PAs/LNAs of antenna elements are tuned for refining the beam codebooks. Strength of a signal, received through different RX beams, is determined based on RSRP/SINR associated with the different RX beams. A direction is determined, along which RSRPs/SINRs associated with consecutive RX beams is increasing. A pair of RX beams is determined, the RSRP/SINR associated with a first beam being greater than e RSRP/SINR associated with a second beam, and the RSRP/SINR associated with the first beam is the greatest along the determined direction.
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公开(公告)号：US12119858B2
公开(公告)日：2024-10-15
申请号：US17696214
申请日：2022-03-16
发明人： Hyun Seok Yu , Hae-Dong Yeon , Gang Minh Lee
IPC分类号： H04B1/3827 , H04B17/318 , H04W52/24 , H04W52/36
CPC分类号： H04B1/3838 , H04B17/318 , H04W52/242 , H04W52/367
摘要： A data transmission device and a data transmission method are provided. The data transmission device includes: a plurality of front-end modules associated with a plurality of antennas, respectively; and a controller configured to select a front-end module to be used for data communication from among the plurality of front-end modules, wherein the controller is configured to: determine a temperature of each of the plurality of front-end modules; and select, from among the plurality of front-end modules, a front-end module having a temperature lower than or equal to a threshold temperature and corresponding to a maximum received power of a receiving device, among received powers of the receiving device corresponding to the plurality of front-end modules, and wherein each of the received powers of the receiving device is obtained based on a specific absorption rate (SAR) requirement or a maximum permissible exposure (MPE) requirement of a corresponding front-end module.
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133.发明授权公开(公告)号：US12119443B2
公开(公告)日：2024-10-15
申请号：US18119927
申请日：2023-03-10
发明人： Yan Wang , Lincoln Miara
IPC分类号： H01M10/0562 , H01M4/04 , H01M4/131 , H01M4/134 , H01M4/1391 , H01M4/1395 , H01M4/36 , H01M4/66 , H01M10/0525 , H01M4/02
CPC分类号： H01M10/0562 , H01M4/0471 , H01M4/131 , H01M4/134 , H01M4/1391 , H01M4/1395 , H01M4/364 , H01M4/661 , H01M4/667 , H01M10/0525 , H01M2004/027 , H01M2004/028
摘要： A solid-state ion conductor includes a compound of Formula 1:
Li16+(5−n)*a−(2+m)*bM2−aXnaN8O1−bAmb Formula 1
wherein, in Formula 1, M is Ta, Nb, V, or a combination thereof, X is an element having an oxidation state of n, wherein n is +1, +2, +3, +4, or a combination thereof, A is an element having an oxidation state of m, wherein m is −1, −2, or a combination thereof, and 0-
公开(公告)号：US12119431B2
公开(公告)日：2024-10-15
申请号：US18236105
申请日：2023-08-21
发明人： Seongmin Kim , Jeongeun Yun , Jeongrok Oh , Sungwoo Choi , Chulsoo Yoon
IPC分类号： H01L33/50 , F21V8/00 , H01L25/075
CPC分类号： H01L33/504 , G02B6/0073 , H01L25/0753 , H01L33/505
摘要： A light emitting device includes a first light emitter including a first light emitting chip emitting first blue light and at least one among a first phosphor and a second phosphor, the first light emitter being configured to emit second blue light, and a second light emitter including a second light emitting chip emitting third blue light and at least one among a third phosphor and a fourth phosphor, the second light emitter being configured to emit fourth blue light, wherein a ratio of an intensity of a peak wavelength of the fourth blue light to an intensity of a peak wavelength of the second blue light is greater than or equal to 0.6.
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公开(公告)号：US12119336B2
公开(公告)日：2024-10-15
申请号：US17883682
申请日：2022-08-09
发明人： Hyunmog Park , Daehyun Kim , Jinmin Kim , Hei Seung Kim , Hyunsik Park , Sangkil Lee
IPC分类号： H01L25/18 , G11C14/00 , G11C16/04 , H01L23/48 , H01L23/522 , H01L25/00 , H10B41/00 , H10B41/27 , H10B43/27 , G11C13/00 , H10B41/41
CPC分类号： H01L25/18 , G11C14/0018 , G11C16/04 , H01L23/481 , H01L23/5226 , H01L25/50 , H10B41/27 , H10B43/27 , G11C13/0004 , H10B41/41
摘要： Disclosed are fusion memory devices and methods of fabricating the same. The fusion memory device comprises a first memory device including a first substrate having active and inactive surfaces opposite to each other and a first memory cell circuit on the active surface of the first substrate, a non-memory device including a second substrate having active and inactive surfaces opposite to each other and a non-memory circuit on the active surface of the second substrate, the non-memory device being provided on the first memory device, and a second memory device on the inactive surface of the second substrate and including a second memory cell circuit different from the first memory cell circuit. The non-memory device lies between the first and second memory cell circuits and controls an electrical operation of each of the first and second memory cell circuits.
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公开(公告)号：US12119329B2
公开(公告)日：2024-10-15
申请号：US18448284
申请日：2023-08-11
发明人： Eunkyul Oh , Yunrae Cho , Taeheon Kim , Seunghun Han
IPC分类号： H01L23/00 , H01L21/56 , H01L21/66 , H01L21/768 , H01L21/78 , H01L23/48 , H01L25/00 , H01L25/065 , H01L25/18
CPC分类号： H01L25/0657 , H01L21/565 , H01L21/76898 , H01L21/78 , H01L22/12 , H01L22/32 , H01L23/481 , H01L24/14 , H01L25/18 , H01L25/50 , H01L2224/14517 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586 , H01L2225/06596
摘要： The present disclosure relates to a semiconductor package and a manufacturing method thereof. The method includes stacking semiconductor chips using a thermo-compression bonding (TCB) method, where defects are minimized for increased reliability. The semiconductor package includes an interface chip including a first test pad, a bump pad provided inside the first test pad, and a first through silicon via (TSV) provided between the first test pad and the bump pad; at least one memory chip, which is stacked on the interface chip and includes a second test pad, a dummy pad provided inside the second test pad, and a second TSV provided between the second test pad and the dummy pad; and an adhesive layer provided between the interface chip and the at least one memory chip. wherein no bump is provided on the first test pad and the second test pad.
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公开(公告)号：US12119288B2
公开(公告)日：2024-10-15
申请号：US17658614
申请日：2022-04-08
发明人： Youngbae Kim , Sungwoo Park
IPC分类号： H01L23/495 , H01L23/00 , H01L23/31
CPC分类号： H01L23/4951 , H01L23/49548 , H01L24/16 , H01L23/3107 , H01L23/49513 , H01L24/14 , H01L2224/1415 , H01L2224/16258
摘要： A semiconductor package includes: a lead frame that includes a first surface and a second surface opposite to the first surface, where the lead frame includes a first lead that extends in a first direction, and a plurality of second leads that are spaced apart from the first lead on both sides of the first lead; at least one semiconductor chip mounted on the first surface of the lead frame by a plurality of bumps; and an encapsulant that encapsulates the lead frame and the at least one semiconductor chip, wherein the first lead has a groove in the first surface that partitions the plurality of bumps in contact with the first lead.
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公开(公告)号：US12119248B2
公开(公告)日：2024-10-15
申请号：US18183520
申请日：2023-03-14
发明人： Taegeon Kim
IPC分类号： H01L21/673
CPC分类号： H01L21/67333
摘要： A module tray for a semiconductor device includes a case and an insert block. The case includes a base plate, first and second sidewalls extending from opposite sides of the base plate in a vertical direction to define an accommodation space, and first and second fastening grooves respectively formed in inner surfaces of the first and second sidewalls. The first and second fastening grooves have upper ends opened to upper surfaces of the first and second sidewalls, respectively. The insert block has a substrate accommodating space for accommodating a semiconductor substrate. The insert block is detachably inserted into the first and second fastening grooves of the case. The insert block has first and second fastening joints extending in the vertical direction such that the first and second fastening joint are respectively inserted through the upper ends of the first and second fastening grooves.
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公开(公告)号：US12119044B2
公开(公告)日：2024-10-15
申请号：US18052644
申请日：2022-11-04
发明人： Seongjin Cho
IPC分类号： G11C11/40 , G11C11/406 , G11C11/4078 , G11C11/4096
CPC分类号： G11C11/4078 , G11C11/40615 , G11C11/40622 , G11C11/4096
摘要： Memory devices and methods for controlling a row hammer are provided. The memory device includes a memory cell array including a word line and a plurality of counter memory cells storing an access count value of the word line, and a control logic circuit configured to monitor a row address accessing the word line during a row hammer monitoring time frame and to determine the row address to be a row hammer address when the number of times the word line is accessed is greater than or equal to a threshold value, wherein the row hammer address is to be stored in an address storage. The control logic circuit is further configured to hold up a determination operation for a next row hammer address, based on activation of a latch full signal indicating that there is no free space to store the row hammer address in the address storage.
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公开(公告)号：US12119036B2
公开(公告)日：2024-10-15
申请号：US18096089
申请日：2023-01-12
CPC分类号： G11C11/1673 , G11C11/1675 , H10B61/00 , H10N50/80
摘要： A magnetic memory device may include a magnetic track, which is extended in a first direction, and a first electrode, which is provided at a biasing point of the magnetic track and is configured to apply a voltage to the magnetic track. The magnetic track includes a first region between a first end of the magnetic track and the biasing point and a second region between the biasing point and a second end of the magnetic track. The first electrode may be configured to cause a difference between a current density in the first region and a current density in the second region.
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