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    CONTACT TRENCH BETWEEN STACKED SEMICONDUCTOR SUBSTRATES
    134.
    发明申请
    CONTACT TRENCH BETWEEN STACKED SEMICONDUCTOR SUBSTRATES 有权

    公开(公告)号：US20180090435A1

    公开(公告)日：2018-03-29

    申请号：US15275619

    申请日：2016-09-26

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Francois Roy

    IPC: H01L23/522 ,  H01L25/065

    CPC classification number: H01L23/5226 ,  H01L25/0657

    Abstract: A first semiconductor substrate layer supports a first transistor including a first source-drain formed by a doped region of the substrate layer. A second semiconductor substrate layer supports a second transistor including a second source-drain formed by a doped region of the substrate layer. The second semiconductor substrate layer is stacked over the first semiconductor substrate layer and separated therefrom by an insulating layer. A metal wiring extends from an electrical contact with the doped region for the first source-drain, through the insulating layer and passing through an electrical isolation structure in the second semiconductor substrate layer to make an electrical contact with the doped region for the second source-drain. The electrical isolation structure is formed by one of a trench isolation or the doped region of the second source-drain itself. The isolation structure has a thickness equal to a thickness of the second semiconductor substrate layer.

    VERTICAL TRANSFER GATE TRANSISTOR AND ACTIVE CMOS IMAGE SENSOR PIXEL INCLUDING A VERTICAL TRANSFER GATE TRANSISTOR
    137.
    发明申请
    VERTICAL TRANSFER GATE TRANSISTOR AND ACTIVE CMOS IMAGE SENSOR PIXEL INCLUDING A VERTICAL TRANSFER GATE TRANSISTOR 审中-公开

    公开(公告)号：US20180061875A1

    公开(公告)日：2018-03-01

    申请号：US15251745

    申请日：2016-08-30

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Francois Roy

    IPC: H01L27/146 ,  H04N5/225

    CPC classification number: H01L27/14614 ,  H01L27/14689

    Abstract: A transfer gate transistor includes a semiconductor substrate including a charge collection source region, a portion forming a channel region and a top region forming a drain region. A trench in the substrate surrounds the top region and the portion of the substrate. A vertical insulated gate structure for the transistor is formed in the trench. The vertical insulated gate structure includes an insulating liner on sidewalls and a bottom of said trench and an electrode including an upper conductive part and a lower conductive part. A width of the upper conductive part parallel to an upper surface of the substrate increases as depth from the upper surface of the substrate increases. A thickness of the insulating liner adjacent the upper conductive part decreases as depth from the upper surface of the substrate increases. A thickness of the insulating liner adjacent the lower conductive part is substantially constant.

    METHOD FOR CHARACTERIZATION OF PHOTONIC DEVICES, AND ASSOCIATED DEVICE
    138.
    发明申请
    METHOD FOR CHARACTERIZATION OF PHOTONIC DEVICES, AND ASSOCIATED DEVICE 审中-公开

    公开(公告)号：US20180031443A1

    公开(公告)日：2018-02-01

    申请号：US15460425

    申请日：2017-03-16

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Patrick Le Maitre ,  Jean-Francois Carpentier

    IPC: G01M11/00

    CPC classification number: G01M11/33 ,  G01M11/30 ,  H04B10/07

    Abstract: An intermediate signal is separated into a first sub-signal and a second sub-signal according to a separation coefficient having a known real value. The first sub-signal is delivered to a first photonic circuit containing at least one photonic device to be characterized and a first photonic part. The second sub-signal is delivered to a second photonic circuit containing a second photonic part having a same transfer function as the first photonic part but lacking the at least one photonic device. Optical output signals from the first and second photonic circuits are converted into first and second electrical signals. Losses of the at least one photonic device are determined from processing the electrical signals and from the known real value of the separation coefficient.

    IMAGE SENSOR OF GLOBAL SHUTTER TYPE
    140.
    发明申请
    IMAGE SENSOR OF GLOBAL SHUTTER TYPE 审中-公开

    公开(公告)号：US20170353673A1

    公开(公告)日：2017-12-07

    申请号：US15358737

    申请日：2016-11-22

    Applicant: STMicroelectronics (Crolles 2) SAS

    Inventor： Francois Roy

    IPC: H04N5/353 ,  H01L27/146 ,  H04N5/378 ,  H04N5/372 ,  H04N5/363

    CPC classification number: H04N5/353 ,  H01L27/14614 ,  H01L27/1464 ,  H01L27/14643 ,  H04N5/363 ,  H04N5/372 ,  H04N5/378

    Abstract: Each pixel of a global shutter back-side illuminated image sensor includes a photosensitive area. On a front surface, a first transistor includes a vertical ring-shaped electrode penetrating into the photosensitive area and laterally delimiting a memory area. The memory area penetrates into the photosensitive area less deeply than the insulated vertical ring-shaped electrode. A read area is formed in an intermediate area which is formed in the memory area. The memory area, the intermediate area and read area define a second transistor having an insulated horizontal electrode forming a gate of the second transistor. The memory area may be formed by a first and second memory areas and an output signal is generated indicative of a difference between charge stored in the first memory area and charge stored in the second memory area after a charge transfer to the first memory area.

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