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257 条记录 (耗时 0.038 秒)

    Method and apparatus for selectively removing anti-stiction coating
    132.
    发明授权
    Method and apparatus for selectively removing anti-stiction coating 有权
    用于选择性去除抗静电涂层的方法和装置

    公开(公告)号：US08728845B2

    公开(公告)日：2014-05-20

    申请号：US13071334

    申请日：2011-03-24

    申请人： Shih-Wei Lin ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Jung-Huei Peng ,  Chia-Shiung Tsai

    发明人： Shih-Wei Lin ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Jung-Huei Peng ,  Chia-Shiung Tsai

    IPC分类号： H01L21/56

    CPC分类号： B81B3/0005 ,  B81C1/00269

    摘要： The present disclosure provides various methods for removing an anti-stiction layer. An exemplary method includes forming an anti-stiction layer over a substrate, including over a first substrate region of a first material and a second substrate region of a second material, wherein the second material is different than the first material; and selectively removing the anti-stiction layer from the second substrate region of the second material without using a mask.

    摘要翻译： 本公开提供了用于去除抗静电层的各种方法。 一种示例性方法包括在衬底上形成抗静电层，包括在第一材料的第一衬底区域和第二材料的第二衬底区域上，其中第二材料不同于第一材料; 并且不使用掩模，从第二材料的第二基板区域选择性地去除抗静电层。

    Spacer structure for transistor device and method of manufacturing same
    134.
    发明授权
    Spacer structure for transistor device and method of manufacturing same 有权
    晶体管器件的间隔结构及其制造方法

    公开(公告)号：US08501572B2

    公开(公告)日：2013-08-06

    申请号：US12874362

    申请日：2010-09-02

    申请人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    发明人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    IPC分类号： H01L21/331

    CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/66287 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7378

    摘要： The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.

    摘要翻译： 本公开提供了一种双极结型晶体管（BJT）器件和用于制造BJT器件的方法。 在一个实施例中，BJT器件包括：具有集电极区域和设置在半导体层上的材料层的半导体衬底。 材料层在其中具有暴露出集电极区域的一部分的沟槽。 基底结构，间隔物和发射体结构设置在材料层的沟槽内。 每个间隔物具有顶部宽度和底部宽度，顶部宽度基本上等于底部宽度。

    Method for forming MTJ cells
    135.
    发明授权
    Method for forming MTJ cells 有权
    形成MTJ细胞的方法

    公开(公告)号：US08278122B2

    公开(公告)日：2012-10-02

    申请号：US12696771

    申请日：2010-01-29

    申请人： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    发明人： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

    IPC分类号： H01L21/00

    CPC分类号： H01L43/12 ,  H01L27/222

    摘要： A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.

    摘要翻译： 形成集成电路结构的方法包括在衬底上形成底电极层; 在底部电极层上形成磁隧道结（MTJ）层; 图案化MTJ层以形成MTJ堆叠; 形成覆盖所述MTJ叠层的电介质层; 在所述电介质层中形成开口以暴露所述MTJ堆叠的一部分; 用顶部电极材料填充开口; 并对顶部电极材料进行平面化。 在执行平面化的步骤之后，对顶部电极材料和电介质层进行图案化，其中开口中的顶部电极材料的第一部分形成顶部电极，并且顶部电极材料的第二部分形成金属带 电介质层并连接到顶部电极。

    METHOD AND APPARATUS FOR SELECTIVELY REMOVING ANTI-STICTION COATING
    136.
    发明申请
    METHOD AND APPARATUS FOR SELECTIVELY REMOVING ANTI-STICTION COATING 有权
    用于选择性去除防粘涂层的方法和装置

    公开(公告)号：US20120244677A1

    公开(公告)日：2012-09-27

    申请号：US13071334

    申请日：2011-03-24

    申请人： Shih-Wei Lin ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Jung-Huei Peng ,  Chia-Shiung Tsai

    发明人： Shih-Wei Lin ,  Ping-Yin Liu ,  Lan-Lin Chao ,  Jung-Huei Peng ,  Chia-Shiung Tsai

    IPC分类号： H01L21/762

    CPC分类号： B81B3/0005 ,  B81C1/00269

    摘要： The present disclosure provides various methods for removing an anti-stiction layer. An exemplary method includes forming an anti-stiction layer over a substrate, including over a first substrate region of a first material and a second substrate region of a second material, wherein the second material is different than the first material; and selectively removing the anti-stiction layer from the second substrate region of the second material without using a mask.

    摘要翻译： 本公开提供了用于去除抗静电层的各种方法。 一种示例性方法包括在衬底上形成抗静电层，包括在第一材料的第一衬底区域和第二材料的第二衬底区域上，其中第二材料不同于第一材料; 并且不使用掩模，从第二材料的第二基板区域选择性地去除抗静电层。

    Method and Apparatus for Forming a III-V Family Layer
    137.
    发明申请
    Method and Apparatus for Forming a III-V Family Layer 审中-公开
    用于形成III-V族层的方法和装置

    公开(公告)号：US20120238076A1

    公开(公告)日：2012-09-20

    申请号：US13482029

    申请日：2012-05-29

    申请人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

    发明人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

    IPC分类号： H01L21/20

    CPC分类号： C23C16/303 ,  C23C16/4401 ,  C23C16/54 ,  C23C16/56

    摘要： Provided is an apparatus. The apparatus includes: a first deposition component that is operable to form a compound over a semiconductor wafer, the compound including at least one of: a III-family element and a V-family element; a second deposition component that is operable to form a passivation layer over the compound; and a transfer component that is operable to move the semiconductor wafer between the first and second deposition components, the transfer component enclosing a space that contains substantially no oxygen and substantially no silicon; wherein the loading component, the first and second deposition components, and the transfer component are all integrated into a single fabrication tool.

    摘要翻译： 提供了一种装置。 该装置包括：第一沉积部件，其可操作以在半导体晶片上形成化合物，所述化合物包括III族元素和V族元素中的至少一种; 第二沉积组分，其可操作以在所述化合物上形成钝化层; 以及可操作以在所述第一和第二沉积部件之间移动所述半导体晶片的转移部件，所述转移部件包围基本上不含氧且基本上不含硅的空间; 其中装载部件，第一和第二沉积部件以及传送部件都被集成到单个制造工具中。

    MRAM cell structure
    138.
    发明申请
    MRAM cell structure 有权
    MRAM单元结构

    公开(公告)号：US20120170358A1

    公开(公告)日：2012-07-05

    申请号：US13308065

    申请日：2011-11-30

    申请人： Jhon Jhy Liaw ,  Yu-Jen Wang ,  Chia-Shiung Tsai

    发明人： Jhon Jhy Liaw ,  Yu-Jen Wang ,  Chia-Shiung Tsai

    IPC分类号： G11C11/16 ,  H01L29/82 ,  H01L21/8246

    CPC分类号： H01L43/12 ,  B82Y10/00 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  H01L27/228 ,  H01L43/08

    摘要： Disclosed herein is an improved memory device, and related methods of manufacturing, wherein the area occupied by a conventional landing pad is significantly reduced to around 50% to 10% of the area occupied by conventional landing pads. This is accomplished by removing the landing pad from the cell structure, and instead forming a conductive via structure that provides the electrical connection from the memory stack or device in the structure to an under-metal layer. By forming only this via structure, rather than separate vias formed on either side of a landing pad, the overall width occupied by the connective via structure from the memory stack to an under-metal layer is substantially reduced, and thus the via structure and under-metal layer may be formed closer to the memory stack (or conductors associated with the stack) so as to reduce the overall width of the cell structure.

    摘要翻译： 这里公开了一种改进的存储器件和相关的制造方法，其中传统的着陆焊盘占据的面积显着地减少到传统的着陆焊盘占据的面积的大约50％到10％。 这是通过从电池结构中移除着陆焊盘而实现的，而是形成导电通孔结构，其提供从结构中的存储器堆或器件到下金属层的电连接。 通过仅形成该通孔结构，而不是形成在着陆焊盘的任一侧上的分离的通孔，结构通孔结构从存储器堆叠到下金属层占据的总宽度大大减小，因此通孔结构和下面 金属层可以形成为更靠近存储器堆叠（或与堆叠相关联的导体），以便减小电池结构的整体宽度。