公开(公告)号：US20160218215A1

公开(公告)日：2016-07-28

申请号：US14953574

申请日：2015-11-30

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Junli Wang ,  Nicolas J. Loubet

IPC: H01L29/78 ,  H01L29/10 ,  H01L27/092 ,  H01L29/165 ,  H01L29/423

CPC classification number: H01L29/6681 ,  H01L21/26506 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66545 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a first region of the cSiGe layer so as to expose a second region of the cSiGe layer; subjecting the exposed second region of the cSiGe layer to an implant process so as to amorphize a bottom portion thereof and transform the cSiGe layer in the second region to a relaxed SiGe (rSiGe) layer; performing an annealing process so as to recrystallize the rSiGe layer; epitaxially growing a tensile strained silicon layer on the rSiGe layer; and patterning fin structures in the tensile strained silicon layer and in the first region of the cSiGe layer.

公开(公告)号：US09391155B2

公开(公告)日：2016-07-12

申请号：US14953908

申请日：2015-11-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Chiahsun Tseng ,  Chun-Chen Yeh ,  Yunpeng Yin

IPC: H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/4966 ,  H01L21/0337 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: In one embodiment, a semiconductor device is provided that includes a gate structure present on a channel portion of a fin structure. The gate structure includes a dielectric spacer contacting a sidewall of a gate dielectric and a gate conductor. Epitaxial source and drain regions are present on opposing sidewalls of the fin structure, wherein surfaces of the epitaxial source region and the epitaxial drain region that is in contact with the sidewalls of the fin structure are aligned with an outside surface of the dielectric spacer. In some embodiments, the dielectric spacer, the gate dielectric, and the gate conductor of the semiconductor device are formed using a single photoresist mask replacement gate sequence.

公开(公告)号：US20160190288A1

公开(公告)日：2016-06-30

申请号：US14743504

申请日：2015-06-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L29/66 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L29/0653 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method further includes forming under a first set of conditions an enriched upper portion of the at least one fin. The method further includes forming under a second set of conditions an electrically isolated region from a lower portion of the at least one fin, wherein forming under the first set of conditions is spaced in time from forming under the second set of conditions. The method further includes controlling the first set of conditions separately from the second set of conditions.

Abstract translation: 实施例涉及一种对FinFET的鳍进行富集和电绝缘的方法。 该方法包括形成至少一个翅片。 所述方法还包括在第一组条件下形成所述至少一个翅片的富集的上部部分。 所述方法还包括在第二组条件下形成与所述至少一个翅片的下部分的电隔离区域，其中在所述第一组条件下的形成与所述第二组条件下的成形间隔开。 该方法还包括与第二组条件分开地控制第一组条件。

公开(公告)号：US09379218B2

公开(公告)日：2016-06-28

申请号：US14584790

申请日：2014-12-29

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/7851

Abstract: A method of forming a semiconductor device that includes forming a silicon including fin structure and forming a germanium including layer on the silicon including fin structure. Germanium is then diffused from the germanium including layer into the silicon including fin structure to convert the silicon including fin structure to silicon germanium including fin structure.

Abstract translation: 一种形成半导体器件的方法，包括在包括鳍结构的硅上形成包括鳍结构的硅并形成含锗层。 然后，锗从含锗层扩散到包括鳍结构的硅中，以将包括鳍结构的硅转化为包括鳍结构的硅锗。

公开(公告)号：US09368350B1

公开(公告)日：2016-06-14

申请号：US14747487

申请日：2015-06-23

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Chi-Chun Liu ,  Alexander Reznicek ,  Chiahsun Tseng ,  Tenko Yamashita

IPC: H01L21/302 ,  H01L21/033 ,  H01L21/027

CPC classification number: H01L21/0337 ,  H01L21/0271 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/0335 ,  H01L21/0338 ,  H01L29/0657

Abstract: A method for DSA fin patterning includes forming a BCP layer over a lithographic stack, the BCP layer having first and second blocks, the lithographic stack disposed over a hard mask and substrate, and the hard mask including first and second dielectric layers; removing the first block to define a fin pattern in the BCP layer with the second block; etching the fin pattern into the first dielectric layer; filling the fin pattern with a tone inversion material; etching back the tone inversion material that overfills the fin pattern; removing the first dielectric layer selectively to define an inverted fin pattern from the tone inversion material; etching the inverted fin pattern into the second dielectric layer of the hard mask; removing the tone inversion material; and transferring the inverted fin pattern of the second dielectric layer into the substrate to define fins.

Abstract translation: 一种用于DSA鳍图形化的方法包括在光刻叠层上形成BCP层，所述BCP层具有第一和第二块，所述光刻堆叠设置在硬掩模和衬底上，并且所述硬掩模包括第一和第二电介质层; 移除所述第一块以在所述BCP层中与所述第二块定义鳍图案; 将鳍状图案蚀刻到第一介电层中; 用色调反转材料填充翅片图案; 蚀刻过度填充鳍图案的色调反转材料; 从所述色调反转材料中选择性地去除所述第一介质层以限定反转的翅片图案; 将倒置的翅片图案蚀刻到硬掩模的第二介电层中; 去除色调反转材料; 并将第二介电层的倒置鳍状图案转印到基板中以限定翅片。

公开(公告)号：US09331148B1

公开(公告)日：2016-05-03

申请号：US14962194

申请日：2015-12-08

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Sivananda K. Kanakasabapathy ,  Gauri Karve ,  Fee Li Lie

IPC: H01L29/10 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/306 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/2253 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for fabricating a semiconductor device, the method comprises forming a fin on a substrate, forming a dummy gate stack on the fin and the substrate, removing a portion of an exposed portion of the fin, forming a source/drain region on an exposed portion of the fin, forming a conductive contact on the source/drain region, removing the dummy gate stack to expose a channel region of the fin, implanting ions in the channel region of the fin, performing an annealing process, and forming a gate stack on the channel region of the fin.

Abstract translation: 一种制造半导体器件的方法，所述方法包括在衬底上形成翅片，在鳍片和衬底上形成虚拟栅极堆叠，去除鳍片的暴露部分的一部分，在曝光的部分上形成源极/漏极区域 在所述源极/漏极区域上形成导电接触，去除所述伪栅极堆叠以暴露所述鳍片的沟道区域，在所述鳍片的沟道区域中注入离子，执行退火处理，以及形成栅极叠层 在翅片的通道区域上。

公开(公告)号：US20160027806A1

公开(公告)日：2016-01-28

申请号：US14874388

申请日：2015-10-03

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek ,  Soon-Cheon Seo

IPC: H01L27/12 ,  H01L29/16 ,  H01L29/04

CPC classification number: H01L27/1211 ,  H01L21/823412 ,  H01L29/04 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.

公开(公告)号：US20150287614A1

公开(公告)日：2015-10-08

申请号：US14581135

申请日：2014-12-23

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Chiahsun Tseng ,  Chun-chen Yeh ,  Yunpeng Yin

IPC: H01L21/321 ,  H01L27/092 ,  H01L21/22 ,  H01L21/8238 ,  H01L29/165

CPC classification number: H01L27/0924 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A cladding layer is epitaxially grown on a portion of the at least one semiconductor fin. The cladding layer is oxidized such that r such that ions are condensed therefrom and are diffused into the at least one semiconductor fin while the cladding layer is converted to an oxide layer. The oxide layer is removed to expose the at least one semiconductor fin having a diffused fin portion that enhances electron hole mobility therethrough.

Abstract translation: 制造半导体器件的方法包括在半导体衬底上形成至少一个半导体鳍片。 在所述至少一个半导体鳍片的一部分上外延生长覆层。 包覆层被氧化成使得离子从其中冷凝并扩散到至少一个半导体翅片中，同时将包层转化为氧化物层。 去除氧化物层以暴露具有增强电子空穴迁移率的扩散翅片部分的至少一个半导体鳍片。

公开(公告)号：US20150228780A1

公开(公告)日：2015-08-13

申请号：US14174914

申请日：2014-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Alexander Reznicek ,  Soon-Cheon Seo

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/1211 ,  H01L21/823412 ,  H01L29/04 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A plurality of semiconductor fins is formed on a surface of an insulator layer. Gate structures are then formed that are orientated perpendicular and straddle each semiconductor fin. A dielectric spacer is then formed on vertical sidewalls of each gate structure. Next, an etch is performed that removes exposed portions of each semiconductor fin and a portion of the insulator layer not protected by the dielectric spacers and the gate structures. The etch provides semiconductor fin portions that have exposed vertical sidewalls. A doped semiconductor material is then formed from each exposed vertical sidewall of each semiconductor fin portion, followed by an anneal which causes diffusion of dopants from the doped semiconductor material into each semiconductor fin portion and the formation of source/drain regions. The source/drain regions are present along the sidewalls of each semiconductor fin portion and are located beneath the dielectric spacers.

Abstract translation: 在绝缘体层的表面上形成多个半导体散热片。 然后形成定向垂直并跨越每个半导体鳍片的栅极结构。 然后在每个栅极结构的垂直侧壁上形成电介质间隔物。 接下来，执行蚀刻，其去除每个半导体鳍片的暴露部分和不被电介质间隔物和栅极结构保护的绝缘体层的一部分。 蚀刻提供具有暴露的垂直侧壁的半导体鳍部分。 然后从每个半导体鳍片部分的每个暴露的垂直侧壁形成掺杂的半导体材料，随后进行退火，其导致掺杂剂从掺杂半导体材料扩散到每个半导体鳍片部分中并形成源极/漏极区域。 源极/漏极区域沿着每个半导体鳍片部分的侧壁存在并且位于电介质间隔物的下方。

公开(公告)号：US20150108572A1

公开(公告)日：2015-04-23

申请号：US14058341

申请日：2013-10-21

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Hong He ,  Chiahsun Tseng ,  Yunpeng Yin

IPC: H01L27/12 ,  H01L21/8234

CPC classification number: H01L21/845 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7831

Abstract: A silicon germanium alloy layer is formed on a semiconductor material layer by epitaxy. An oxygen impermeable layer is formed on the silicon germanium alloy layer. The oxygen impermeable layer and the silicon germanium alloy layer are patterned to form stacks of a silicon germanium alloy fin and an oxygen impermeable cap. A shallow trench isolation structure is formed by deposition, planarization, and recessing or an oxygen permeable dielectric material. An oxygen impermeable spacer is formed around each stack of a silicon germanium alloy fin and an oxygen impermeable cap. A thermal oxidation process is performed to convert a lower portion of each silicon germanium alloy fin into a silicon germanium oxide. During the thermal oxidation process, germanium atoms diffuse into unoxidized portions of the silicon germanium alloy fins to increase the germanium concentration therein.

Abstract translation: 通过外延在半导体材料层上形成硅锗合金层。 在硅锗合金层上形成不透氧层。 对不透氧层和硅锗合金层进行图案化以形成硅锗合金翅片和不透氧盖的叠层。 通过沉积，平坦化和凹陷形成浅沟槽隔离结构或透氧介电材料。 在硅锗合金翅片和不透氧盖的每个堆叠周围形成不透氧隔离物。 进行热氧化处理以将每个硅锗合金翅片的下部转换成硅氧化锗。 在热氧化过程中，锗原子扩散到硅锗合金翅片的未氧化部分，以增加其中的锗浓度。