公开(公告)号：US20180218872A1

公开(公告)日：2018-08-02

申请号：US15801881

申请日：2017-11-02

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu

IPC: H01J21/08 ,  H01J9/18 ,  H01J9/39 ,  H01J19/42 ,  H01L41/09 ,  H01L41/047 ,  H01L41/29

Abstract: A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.

公开(公告)号：US20180218871A1

公开(公告)日：2018-08-02

申请号：US15418807

申请日：2017-01-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu

IPC: H01J21/08 ,  H01L41/047 ,  H01L41/09 ,  H01L41/29 ,  H01J19/42 ,  H01J9/39 ,  H01J9/18

Abstract: A vacuum transistor includes a substrate and a first terminal formed on the substrate. A piezoelectric element has a second terminal formed on the piezoelectric element, wherein the piezoelectric element is provided over the first terminal to provide a gap between the first terminal and the second terminal. The gap is adjusted in accordance with an electrical field on the piezoelectric element.

公开(公告)号：US10032897B2

公开(公告)日：2018-07-24

申请号：US15170448

申请日：2016-06-01

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu

IPC: H01L21/306 ,  H01L21/02 ,  H01L29/76 ,  H01L29/423 ,  H01L29/165 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10

Abstract: Semiconductor devices and methods of making the same include forming a gate structure on a thin semiconductor layer. Additional semiconductor material is formed on the thin semiconductor layer. The thin semiconductor layer is etched back and the additional semiconductor material to form source and drain regions and a channel region, with notches separating the source and drain region from the channel region.

公开(公告)号：US09887282B1

公开(公告)日：2018-02-06

申请号：US15277393

申请日：2016-09-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Cao ,  Ning Li ,  Jianshi Tang

IPC: H01L29/778 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/7786 ,  H01L29/401 ,  H01L29/413 ,  H01L29/475 ,  H01L29/49 ,  H01L29/66431 ,  H01L29/7787 ,  H01L29/812

Abstract: A method of forming an electrical device that includes forming ohmic contacts to a type III-V semiconductor substrate, and depositing a dielectric layer on the ohmic contacts and an exposed surface of the type III-V semiconductor substrate. A nanotube is positioned on a surface of the high-k dielectric that is overlying the type III-V semiconductor substrate and is between the ohmic contacts using chemical recognition. The dielectric layer is removed so that the nanotube is repositioned directly on the type III-V semiconductor substrate to provide an Schottky contact to a channel region of the type III-V semiconductor substrate.

公开(公告)号：US20180033864A1

公开(公告)日：2018-02-01

申请号：US15222324

申请日：2016-07-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Cao ,  Ning Li

IPC: H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49

CPC classification number: H01L29/78 ,  H01L27/20 ,  H01L29/1008 ,  H01L29/1606 ,  H01L29/66568 ,  H01L29/66977 ,  H01L29/735 ,  H01L41/18

Abstract: A method is presented for forming a semiconductor device. The method may include forming a source contact on the semiconductor substrate, forming a drain contact on the semiconductor substrate, and forming a gate structure on the semiconductor substrate between the source and drain contacts, the gate structure including a piezoelectric material having at least one graphene layer.

公开(公告)号：US09786851B2

公开(公告)日：2017-10-10

申请号：US15287214

申请日：2016-10-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu ,  Zhen Zhang

IPC: H01L29/775 ,  H01L21/336 ,  H01L51/05 ,  H01L27/28 ,  H01L51/00 ,  B82Y30/00 ,  B82Y10/00 ,  B82Y40/00

CPC classification number: H01L51/055 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L27/283 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/0541 ,  H01L51/0558 ,  H01L51/0566 ,  H01L51/057 ,  H01L51/105 ,  H01L2251/303 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

Abstract: A transistor device includes an array of fin structures arranged on a substrate, each of the fin structures being vertically alternating stacks of a first isoelectric point material having a first isoelectric point and a second isoelectric point material having a second isoelectric point that is different than the first isoelectric point; one or more carbon nanotubes (CNTs) suspended between the fin structures and contacting a side surface of the second isoelectric point material in the fin structures; a gate wrapped around the array of CNTs; and source and drain contacts arranged over the fin structures; wherein each of the fin structures have a trapezoid shape or parallel sides that are oriented about 90° with respect to the substrate.

公开(公告)号：US20170284963A1

公开(公告)日：2017-10-05

申请号：US15623985

申请日：2017-06-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu ,  Zhen Zhang

IPC: G01N27/447 ,  G01N33/487 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/02

Abstract: A sensor includes a semiconductor substrate having first pointed nodes extending into a channel from a first side of the channel. Second pointed nodes extend into the channel from a second side of the channel, which is opposite the first side. The second pointed nodes being self-aligned to the first pointed nodes on the opposite side of the channel. The first pointed nodes and the second pointed nodes are connected to a circuit to detect particles in the channel.

公开(公告)号：US09753006B2

公开(公告)日：2017-09-05

申请号：US14743637

申请日：2015-06-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Cao ,  Kangguo Cheng ,  Zhengwen Li ,  Fei Liu ,  Zhen Zhang

IPC: G01N27/414

CPC classification number: G01N27/44791 ,  G01N27/4146 ,  G01N33/48707 ,  H01L21/02236 ,  H01L21/3065 ,  H01L21/31116

Abstract: A sensor includes a semiconductor substrate having first pointed nodes extending into a channel from a first side of the channel. Second pointed nodes extend into the channel from a second side of the channel, which is opposite the first side. The second pointed nodes being self-aligned to the first pointed nodes on the opposite side of the channel. The first pointed nodes and the second pointed nodes are connected to a circuit to detect particles in the channel.

公开(公告)号：US09691882B2

公开(公告)日：2017-06-27

申请号：US13802986

申请日：2013-03-14

Applicant: International Business Machines Corporation

Inventor： Zhengwen Li ,  Qing Cao ,  Kangguo Cheng ,  Fei Liu ,  Zhen Zhang

IPC: H01L21/70 ,  H01L29/66 ,  H01L29/08 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/12 ,  H01L21/311 ,  H01L21/02 ,  H01L29/45 ,  H01L21/285 ,  H01L21/768

CPC classification number: H01L29/66795 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/28518 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76855 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823871 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/458 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66628

Abstract: After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure. A contact via cavity is formed through the planarization dielectric material layer by an anisotropic etch process that employs a fluorocarbon gas as an etchant. The carbon in the carbon-doped semiconductor material portion retards the anisotropic etch process, and the carbon-doped semiconductor material portion functions as a stopping layer for the anisotropic etch process, thereby making the depth of the contact via cavity less dependent on variations on the thickness of the planarization dielectric layer or pattern factors.

公开(公告)号：US20170133610A1

公开(公告)日：2017-05-11

申请号：US14951847

申请日：2015-11-25

Applicant: International Business Machines Corporation

Inventor： Qing Cao ,  Shu-Jen Han ,  Jianshi Tang

IPC: H01L51/10 ,  H01L51/00 ,  H01L51/05

CPC classification number: H01L51/105 ,  H01L51/0021 ,  H01L51/0026 ,  H01L51/0048 ,  H01L51/0558 ,  H01L2251/301

Abstract: A method of forming an end-bonded contact on a semiconductor is disclosed herein. The method can include forming a dielectric layer on a substrate and depositing a carbon nanotube layer onto the dielectric layer. Additionally, the method can include depositing a resist mask onto the carbon nanotube layer and patterning the resist mask to form a contact mold such that a portion of the carbon nanotube layer is exposed. In some aspects, the method can include depositing a contact metal such that the contact metal contacts the exposed carbon nanotube layer and thermally annealing the device such that the carbon nanotube layer dissolves into the contact metal such that a single contact surface is formed between the contact and the carbon nanotube layer.