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131.发明授权Transistor having a monocrystalline center section and a polycrystalline outer section, and narrow in-substrate collector region for reduced base-collector junction capacitance 有权具有单晶中心部分和多晶外部部分的晶体管，以及用于降低的基极 - 集电极结电容的窄的衬底内集电极区域公开(公告)号：US08786051B2
公开(公告)日：2014-07-22
申请号：US13401064
申请日：2012-02-21
申请人： James W. Adkisson , David L. Harame , Qizhi Liu
发明人： James W. Adkisson , David L. Harame , Qizhi Liu
IPC分类号： H01L21/02
CPC分类号： H01L29/732 , H01L29/1004 , H01L29/66234 , H01L29/66242 , H01L29/7371
摘要： Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.
摘要翻译： 公开了晶体管（例如，双极结型晶体管（BJT）或异质结双极晶体管（HBT））以及形成具有窄的衬底内集电极区域以减小基极 - 集电极结电容的晶体管的方法。 晶体管在衬底内具有位于横向邻近沟槽隔离区域的集电极区域。 相对薄的种子层覆盖沟槽隔离区域和收集器区域。 该晶种层具有单晶中心，该晶体中心在集电极区域上方（例如由于固相外延再生长工艺）而上方且更宽，并且多晶外部部分。 本征基底层外延沉积在种子层上，使得其类似地具有在集电极区域上方并且更宽的单晶中心部分。 非本征基层是本征基层，并且具有从集电极垂直偏移的单晶非本征基本至本征基极连接区域。
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公开(公告)号：US08633055B2
公开(公告)日：2014-01-21
申请号：US13324246
申请日：2011-12-13
IPC分类号： H01L51/40 , H01L21/8232 , H01L21/336 , H01L21/00
CPC分类号： H01L29/1606 , B82Y10/00 , B82Y30/00 , B82Y40/00 , C01B32/186 , H01L27/1222 , H01L29/41733 , H01L29/42384 , H01L29/66045 , H01L29/66742 , H01L29/778 , H01L29/7786 , H01L29/785 , H01L29/78684 , H01L29/78696
摘要： Manufacturing a semiconductor structure including: forming a seed material on a sidewall of a mandrel; forming a graphene field effect transistor (FET) on the seed material; and removing the seed material.
摘要翻译： 制造半导体结构，包括：在心轴的侧壁上形成种子材料; 在种子材料上形成石墨烯场效应晶体管（FET）; 并移除种子材料。
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公开(公告)号：US08492272B2
公开(公告)日：2013-07-23
申请号：US13193991
申请日：2011-07-29
IPC分类号： H01L21/4763 , H01L21/04 , H01L29/40
CPC分类号： H01L21/76898 , H01L21/26586 , H01L29/732
摘要： A method for forming passivated through wafer vias, passivated through wafer via structures, and passivated through wafer via design structures. The method includes: forming a through wafer via in a semiconductor substrate, the through wafer via comprising an electrical conductor extending from a top of the semiconductor substrate to a bottom surface of the semiconductor substrate; and forming a doped layer abutting all sidewalls of the electrical conductor, the doped layer of a same dopant type as the semiconductor substrate, the concentration of dopant in the doped layer greater than the concentration of dopant in the semiconductor substrate, the doped layer intervening between the electrical conductor and the semiconductor substrate.
摘要翻译： 用于形成钝化的晶片通孔的方法，通过晶片通孔结构钝化，并通过设计结构钝化通过晶片。 该方法包括：在半导体衬底中形成贯穿晶片通孔，所述贯通晶片通孔包括从半导体衬底的顶部延伸到半导体衬底的底表面的电导体; 并且形成邻接电导体的所有侧壁的掺杂层，与半导体衬底相同的掺杂剂类型的掺杂层，掺杂层中掺杂剂的浓度大于半导体衬底中掺杂剂的浓度，掺杂层介于 电导体和半导体衬底。
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公开(公告)号：US20130154003A1
公开(公告)日：2013-06-20
申请号：US13329440
申请日：2011-12-19
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1045 , H01L29/66492 , H01L29/66583 , H01L29/6659 , H01L29/66659 , H01L29/7835
摘要： A method of forming an integrated circuit structure implants a first compensating implant into a substrate. The method patterns a mask on the first compensating implant in the substrate. The mask includes an opening exposing a channel location of the substrate. The method implants a second compensating implant into the channel location of the substrate. The second compensating implant is made through the opening in the mask and at an angle that is offset from perpendicular to the top surface of the substrate. The second compensating implant is positioned closer to a first side of the channel location relative to an opposite second side of the channel location and the second compensating implant comprises a material having the same doping polarity as the semiconductor channel implant. Then, the method forms a gate conductor above the channel location of the substrate in the opening of the mask.
摘要翻译： 形成集成电路结构的方法将第一补偿植入物植入衬底。 该方法在衬底中的第一补偿植入物上形成掩模。 掩模包括暴露基板的通道位置的开口。 该方法将第二补偿植入物植入衬底的通道位置。 第二补偿植入物通过掩模中的开口并以与衬底的顶表面垂直的角度形成。 第二补偿植入件相对于沟道位置的相对的第二侧被定位成更靠近通道位置的第一侧，并且第二补偿植入物包括具有与半导体沟道植入物相同的掺杂极性的材料。 然后，该方法在掩模的开口中在衬底的通道位置之上形成栅极导体。
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135.发明申请BIPOLAR TRANSISTOR WITH A RAISED COLLECTOR PEDASTAL FOR REDUCED CAPACITANCE AND A METHOD OF FORMING THE TRANSISTOR 有权具有用于降低电容的集电器底座的双极晶体管和形成晶体管的方法公开(公告)号：US20130134483A1
公开(公告)日：2013-05-30
申请号：US13307412
申请日：2011-11-30
IPC分类号： H01L29/737 , H01L21/331 , H01L29/73
CPC分类号： H01L29/66234 , H01L29/0826 , H01L29/66287 , H01L29/732 , H01L29/7371
摘要： Disclosed are a transistor and a method of forming the transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently, base-collector junction capacitance is reduced and, consequently, the maximum oscillation frequency is increased.
摘要翻译： 公开了晶体管和以缩小的尺寸形成具有凸起的集电极基座的晶体管的方法，以减小基极 - 集电极结电容。 凸起的收集器基座位于基板的顶表面上，垂直延伸穿过绝缘层（未掺杂或低掺杂）在衬底内的子集电极区域上方排列， 收集区域。 本征基层在凸起的收集器基座和介电层之上。 外在基层在本征基层之上。 因此，外部基极层和副集电极区域之间的空间增加。 该增加的空间由电介质材料填充，并且本征基极层和次集电极区域之间的电连接由相对窄的未掺杂或低掺杂的升高的集电极基座提供。 因此，集电极结电容减小，因此最大振荡频率增加。
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公开(公告)号：US20130069199A1
公开(公告)日：2013-03-21
申请号：US13233752
申请日：2011-09-15
CPC分类号： H01L28/90
摘要： A MIM capacitor includes a dielectric cap that enhances performance and reduces damage to MIM insulators during manufacture. A cavity is formed in an insulative substrate, such as a back end of line dielectric layer, and a first metal layer and an insulator layer are conformally deposited. A second metal layer may be deposited conformally and/or to fill a remaining portion of the cavity. The dielectric cap may be an extra layer of insulative material deposited at ends of the insulator at an opening of the cavity and may also be formed as part of the insulator layer.
摘要翻译： MIM电容器包括在制造期间增强性能并减少对MIM绝缘体的损坏的电介质盖。 在绝缘基板（例如线路介质层的后端）中形成空腔，并且第一金属层和绝缘体层被共形沉积。 可以共形地沉积第二金属层和/或填充空腔的剩余部分。 电介质盖可以是在空腔的开口处沉积在绝缘体的端部处的绝缘材料的额外层，并且还可以形成为绝缘体层的一部分。
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公开(公告)号：US08232651B2
公开(公告)日：2012-07-31
申请号：US13343422
申请日：2012-01-04
IPC分类号： H01L23/48
CPC分类号： H01L24/05 , H01L23/3114 , H01L23/485 , H01L23/562 , H01L23/585 , H01L24/03 , H01L2224/05553 , H01L2224/0558 , H01L2224/05624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/1461 , H01L2924/00014 , H01L2924/00
摘要： An electronic packaging having at least one bond pad positioned on a chip for effectuating through-wafer connections to an integrated circuit. The electronic package is equipped with an edge seal between the bond pad region and an active circuit region, and includes a crack stop, which is adapted to protect the arrangement from the entry of deleterious moisture and combination into the active regions of the chip containing the bond pads.
摘要翻译： 一种电子封装，其具有位于芯片上的至少一个接合焊盘，用于实现与集成电路的晶圆连接。 电子封装在接合焊盘区域和有源电路区域之间配备有边缘密封，并且包括裂缝停止件，其适于保护布置免受有害水分和组合进入含有 接合垫
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公开(公告)号：US08227844B2
公开(公告)日：2012-07-24
申请号：US12013817
申请日：2008-01-14
IPC分类号： H01L31/062 , H01L31/113 , H01L27/148 , H01L21/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14612
摘要： A CMOS active pixel sensor (APS) cell structure includes at least one transfer gate device and method of operation. A first transfer gate device comprises a diodic or split transfer gate conductor structure having a first doped region of first conductivity type material and a second doped region of a second conductivity type material. A photosensing device is formed adjacent the first doped region for collecting charge carriers in response to light incident thereto, and, a diffusion region of a second conductivity type material is formed at or below the substrate surface adjacent the second doped region of the transfer gate device for receiving charges transferred from the photosensing device while preventing spillback of charges to the photosensing device upon timed voltage bias to the diodic or split transfer gate conductor structure.
摘要翻译： CMOS有源像素传感器（APS）单元结构包括至少一个传输栅极器件和操作方法。 第一传输栅极器件包括具有第一导电类型材料的第一掺杂区域和第二导电类型材料的第二掺杂区域的二极或分裂传输栅极导体结构。 光敏装置形成在第一掺杂区域附近，用于响应于入射到其上的光而收集电荷载流子，并且第二导电类型材料的扩散区域形成在与传输栅极器件的第二掺杂区域相邻的衬底表面处或下方 用于接收从光敏装置转移的电荷，同时防止在针对二极或分离转移栅极导体结构的定时电压偏压时对光敏装置的电荷溢出。
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公开(公告)号：US20110193146A1
公开(公告)日：2011-08-11
申请号：US13089234
申请日：2011-04-18
IPC分类号： H01L27/146 , H01L31/0216 , H01L31/18
CPC分类号： H01L27/14689 , H01L27/14609 , H01L27/14621 , H01L27/14623 , H01L27/14627 , H01L27/14643
摘要： A pixel sensor structure, method of manufacture and method of operating. Disclosed is a buffer pixel cell comprising a barrier region for preventing stray charge carriers from arriving at a dark current correction pixel cell. The buffer pixel cell is located in the vicinity of the dark current correction pixel cell and the buffer pixel cell resembles an active pixel cell. Thus, an environment surrounding the dark current correction pixel cell is similar to the environment surrounding an active pixel cell.
摘要翻译： 像素传感器结构，制造方法和操作方法。 公开了一种缓冲像素单元，其包括用于防止杂散电荷载流子到达暗电流校正像素单元的阻挡区域。 缓冲像素单元位于暗电流校正像素单元附近，并且缓冲像素单元类似于有源像素单元。 因此，围绕暗电流校正像素单元的环境与有源像素单元周围的环境相似。
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公开(公告)号：US07977711B2
公开(公告)日：2011-07-12
申请号：US12172305
申请日：2008-07-14
申请人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D. Jaffe , Jeffrey B. Johnson , Alain Loiseau
发明人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D. Jaffe , Jeffrey B. Johnson , Alain Loiseau
IPC分类号： H01L27/148 , H01L31/062
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281
摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译： 本发明是像素传感器单元及其制造方法。 像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。 具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上产生的电子以及形成在基板表面下方的p型收集阱区域 用于收集由撞击光子产生的孔。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。
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