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    Contact formation method incorporating preventative etch step reducing interlayer dielectric material flake defects
    3.
    发明授权
    Contact formation method incorporating preventative etch step reducing interlayer dielectric material flake defects 失效
    包含预防性蚀刻步骤的接触形成方法减少层间绝缘材料薄片缺陷

    公开(公告)号：US08691690B2

    公开(公告)日：2014-04-08

    申请号：US12880437

    申请日：2010-09-13

    申请人： Yoba Amoah ,  Brian M. Czabaj ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Molly J. Leitch ,  Polina A. Razina

    发明人： Yoba Amoah ,  Brian M. Czabaj ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Molly J. Leitch ,  Polina A. Razina

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76816 ,  H01L21/0334 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76877

    摘要： Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking.

    摘要翻译： 公开了接合形成技术的实施例，其包括预防性蚀刻步骤以减少层间绝缘材料剥落（例如，硼磷硅玻璃（BPSG）剥落），从而减少表面缺陷。 具体地说，可通过化学气相沉积（CVD）沉积的导体层填充通过电介质层延伸到衬底中部和/或中心部分的半导体器件的接触开口。 可以进行导体层的化学机械抛光（CMP）以完成接触结构。 然而，在执行CMP工艺之前（例如，在形成接触开口之前或在填充接触开口之前），可以执行预防蚀刻工艺以从衬底的边缘部分上方去除任何电介质材料。 在CMP之前从衬底的边缘部分上方去除电介质材料减少了由电介质材料剥落引起的表面缺陷的发生。

    CONTACT FORMATION METHOD INCORPORATING A PREVENTATIVE ETCH STEP FOR REDUCING INTERLAYER DIELECTRIC MATERIAL FLAKE DEFECTS
    4.
    发明申请
    CONTACT FORMATION METHOD INCORPORATING A PREVENTATIVE ETCH STEP FOR REDUCING INTERLAYER DIELECTRIC MATERIAL FLAKE DEFECTS 失效
    联合形成方法包含减少中间层介质材料失火的预防蚀刻步骤

    公开(公告)号：US20120064714A1

    公开(公告)日：2012-03-15

    申请号：US12880437

    申请日：2010-09-13

    申请人： Yoba Amoah ,  Brian M. Czabaj ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Molly J. Leitch ,  Polina A. Razina

    发明人： Yoba Amoah ,  Brian M. Czabaj ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Molly J. Leitch ,  Polina A. Razina

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76816 ,  H01L21/0334 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76877

    摘要： Disclosed are embodiments of a contact formation technique that incorporates a preventative etch step to reduce interlayer dielectric material flaking (e.g., borophosphosilicate glass (BPSG) flaking) and, thereby to reduce surface defects. Specifically, contact openings, which extend through a dielectric layer to semiconductor devices in and/or on a center portion of a substrate, can be filled with a conductor layer deposited by chemical vapor deposition (CVD). Chemical mechanical polishing (CMP) of the conductor layer can be performed to complete the contact structures. However, before the CMP process is performed (e.g., either before the contact openings are ever formed or before the contact openings are filled), a preventative etch process can be performed to remove any dielectric material from above the edge portion of the substrate. Removing the dielectric material from above the edge portion of the substrate prior to CMP reduces the occurrence of surface defects caused by dielectric material flaking.

    摘要翻译： 公开了接合形成技术的实施例，其包括预防性蚀刻步骤以减少层间绝缘材料剥落（例如，硼磷硅玻璃（BPSG）剥落），从而减少表面缺陷。 具体地说，可通过化学气相沉积（CVD）沉积的导体层填充通过电介质层延伸到衬底中部和/或中心部分的半导体器件的接触开口。 可以进行导体层的化学机械抛光（CMP）以完成接触结构。 然而，在执行CMP工艺之前（例如，在形成接触开口之前或在填充接触开口之前），可以执行预防蚀刻工艺以从衬底的边缘部分上方去除任何电介质材料。 在CMP之前从衬底的边缘部分上方去除电介质材料减少了由电介质材料剥落引起的表面缺陷的发生。

    Self-dicing chips using through silicon vias
    10.
    发明授权
    Self-dicing chips using through silicon vias 失效
    通过硅通孔的自切割芯片

    公开(公告)号：US08168474B1

    公开(公告)日：2012-05-01

    申请号：US12987402

    申请日：2011-01-10

    申请人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Yen L. Lim

    发明人： James W. Adkisson ,  Panglijen Candra ,  Thomas J. Dunbar ,  Jeffrey P. Gambino ,  Mark D. Jaffe ,  Robert K. Leidy ,  Yen L. Lim

    IPC分类号： H01L21/00

    CPC分类号： H01L21/78 ,  H01L21/76898

    摘要： Systems and methods simultaneously form first openings and second openings in a substrate. The first openings are formed smaller than the second openings. The method also simultaneously forms a first material in the first openings and the second openings. The first material fills the first openings, and the first material lines the second openings. The method forms a second material different than the first material in the second openings. The second material fills the second openings. The method forms a plurality of integrated circuit structures over the first material and the second material within the second openings. The method applies mechanical stress to the substrate to cause the substrate to split along the first openings.

    摘要翻译： 系统和方法同时在衬底中形成第一开口和第二开口。 第一开口形成为小于第二开口。 该方法还同时在第一开口和第二开口中形成第一材料。 第一材料填充第一开口，第一材料将第二开口排列。 该方法形成与第二开口中的第一材料不同的第二材料。 第二材料填充第二开口。 该方法在第二开口内的第一材料和第二材料上形成多个集成电路结构。 该方法对基板施加机械应力以使基板沿着第一开口分开。