公开(公告)号：US09614584B2

公开(公告)日：2017-04-04

申请号：US14846672

申请日：2015-09-04

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Benjamin Stassen Cook

IPC: H04B1/40 ,  H04B3/52 ,  H01P3/16 ,  H01P5/08

CPC classification number: H04B3/52 ,  H01P3/16 ,  H01P5/087

Abstract: A device is configured for transmitting multiple channels of information through a dielectric waveguide (DWG). The device generates at least a first radio frequency signal (RF) and a second RF signal. The first RF signal is launched into the DWG using a launching structure formed within a multilayer substrate to excite a first transmission mode of the DWG. The second RF signal is launched into the DWG using a launching structure formed within the multilayer substrate to excite a second transmission mode of the DWG, in which the second transmission mode is orthogonal to the first transmission mode.

公开(公告)号：US20160344448A1

公开(公告)日：2016-11-24

申请号：US14846672

申请日：2015-09-04

Applicant: Texas Instruments Incorporated

Inventor： Juan Alejandro Herbsommer ,  Benjamin Stassen Cook

IPC: H04B3/52 ,  H01P3/16

CPC classification number: H04B3/52 ,  H01P3/16 ,  H01P5/087

Abstract: A device is configured for transmitting multiple channels of information through a dielectric waveguide (DWG). The device generates at least a first radio frequency signal (RF) and a second RF signal. The first RF signal is launched into the DWG using a launching structure formed within a multilayer substrate to excite a first transmission mode of the DWG. The second RF signal is launched into the DWG using a launching structure formed within the multilayer substrate to excite a second transmission mode of the DWG, in which the second transmission mode is orthogonal to the first transmission mode.

Abstract translation: 一种器件被配置为通过介质波导（DWG）发送多个信道信道。 该设备至少产生第一射频信号（RF）和第二RF信号。 第一RF信号使用形成在多层基板内的发射结构发射到DWG中，以激发DWG的第一传输模式。 第二RF信号使用形成在多层基板内的发射结构发射到DWG中，以激发DWG的第二传输模式，其中第二传输模式与第一传输模式正交。

公开(公告)号：US12176298B2

公开(公告)日：2024-12-24

申请号：US17115734

申请日：2020-12-08

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Steven Kummerl ,  Kurt Peter Wachtler

IPC: H01L23/31 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/495

Abstract: A floating die package including a cavity formed through sublimation of a sacrificial die encapsulant and sublimation or separation of die attach materials after molding assembly. A pinhole vent in the molding structure is provided as a sublimation path to allow gases to escape, whereby the die or die stack is released from the substrate and suspended in the cavity by the bond wires only.

公开(公告)号：US12042829B2

公开(公告)日：2024-07-23

申请号：US17020625

申请日：2020-09-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Lee Revier ,  Benjamin Stassen Cook ,  David Patrick Magee ,  Stephen John Fedigan

IPC: B08B7/02 ,  F26B5/02 ,  G02B27/00

CPC classification number: B08B7/028 ,  G02B27/00 ,  G02B27/0006 ,  F26B5/02

Abstract: For surface wetting control, an apparatus can expel fluid from a droplet on a surface using a transducer mechanically coupled to the surface. A first area of the surface can have a first wettability for the fluid, and a second area of the surface can have a second wettability for the fluid. The first wettability of the first area of the surface can be greater than the second wettability of the second area of the surface. The first area and the second area can have a patterned arrangement.

公开(公告)号：US20240194574A1

公开(公告)日：2024-06-13

申请号：US18585629

申请日：2024-02-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Yogesh Kumar Ramadass ,  Salvatore Frank Pavone ,  Mahmud Halim Chowdhury

IPC: H01L23/495 ,  H01L23/00

CPC classification number: H01L23/49589 ,  H01L23/4951 ,  H01L23/49524 ,  H01L24/32 ,  H01L24/73 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/92 ,  H01L2224/11462 ,  H01L2224/13147 ,  H01L2224/13564 ,  H01L2224/1357 ,  H01L2224/16245 ,  H01L2224/32265 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/9211 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Disclosed embodiments include an integrated circuit (IC) comprising a silicon wafer, first and second conductive lines on the silicon wafer. There are first, second and third insulation blocks with portions on the first and second conductive lines and the silicon wafer, a metal pillar on the surface of the first conductive line opposite the silicon wafer, and a conductive adhesive block on the surface of the second conductive line opposite the silicon wafer. The IC also has a lead frame having first and second leads, and a capacitor having first and second capacitor terminals in which the first capacitor terminal is connected to the second lead using conductive adhesive, the second capacitor terminal is connected to the second conductive line through the conductive adhesive block, and the first lead is coupled to the first conductive line.

公开(公告)号：US20240153841A1

公开(公告)日：2024-05-09

申请号：US18544590

申请日：2023-12-19

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Archana Venugopal ,  Daniel Lee Revier

IPC: H01L23/373 ,  H01L21/3205 ,  H01L21/683 ,  H01L21/78 ,  H01L23/532

CPC classification number: H01L23/373 ,  H01L21/32051 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/53209

Abstract: In described examples, a method comprises forming a patterned region on a first surface of the semiconductor substrate. The method also comprises forming circuitry in the patterned region. The method further comprises forming a metallic layer on a second surface of the semiconductor substrate, in which the second surface opposes the first surface; and forming a carbon layer on the metallic layer.

公开(公告)号：US20240145526A1

公开(公告)日：2024-05-02

申请号：US18404496

申请日：2024-01-04

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Daniel Lee Revier

IPC: H01F17/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/66

CPC classification number: H01L28/10 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/66 ,  H01L2223/6677

Abstract: In described examples, an integrated circuit comprises: a substrate; a semiconductor die on the substrate; and a device on the substrate and electrically coupled to the semiconductor die, the device including a polymer structure coated with a metal.

公开(公告)号：US20240109247A1

公开(公告)日：2024-04-04

申请号：US18527663

申请日：2023-12-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daniel Lee Revier ,  Sean Ping Chang ,  Benjamin Stassen Cook

IPC: B29C64/165 ,  B22F10/00 ,  B22F10/14 ,  B22F12/37 ,  B22F12/53 ,  B22F12/55 ,  B22F12/57 ,  B28B1/00 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  H01L21/02 ,  H01L21/288 ,  H01L21/67

CPC classification number: B29C64/165 ,  B22F10/00 ,  B22F10/14 ,  B22F12/37 ,  B22F12/53 ,  B22F12/55 ,  B22F12/57 ,  B28B1/001 ,  B33Y10/00 ,  B33Y30/00 ,  B33Y70/00 ,  B33Y80/00 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02288 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/02623 ,  H01L21/288 ,  H01L21/6715 ,  B29L2031/34

Abstract: A layer of additive material is formed in a circular printing area on a substrate using additive sources distributed across a printing zone. The additive sources form predetermined discrete amounts of the additive material. The substrate and the additive sources are rotated with respect to each other around a center of rotation, so that a pattern of the additive material is formed in a circular printing area on the substrate. Each additive source receives actuation waveforms at an actuation frequency that is proportional to a distance of the additive source from the center of rotation. The actuation waveforms include formation signals, with a maximum of one formation signal in each cycle of the actuation frequency. The formation signals result in the additive sources forming the predetermined discrete amounts of the additive material on the substrate.

公开(公告)号：US11938715B2

公开(公告)日：2024-03-26

申请号：US16229668

申请日：2018-12-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Luigi Colombo ,  Nazila Dadvand ,  Benjamin Stassen Cook ,  Archana Venugopal

IPC: B32B9/00 ,  B32B9/04 ,  C01B32/184 ,  C01B32/19 ,  C23C18/32 ,  C23C18/38 ,  H01M50/00 ,  B82Y30/00

CPC classification number: B32B9/007 ,  B32B9/041 ,  B32B9/045 ,  C01B32/184 ,  C01B32/19 ,  C23C18/32 ,  C23C18/38 ,  H01M50/00 ,  B32B2305/38 ,  B32B2457/14 ,  B82Y30/00 ,  C01P2002/20 ,  Y10T428/30

Abstract: A microstructure comprises a plurality of interconnected units wherein the units are formed of graphene tubes. The graphene tubes may be formed by photo-initiating the polymerization of a monomer in a pattern of interconnected units to form a polymer microlattice, removing unpolymerized monomer, coating the polymer microlattice with a metal, removing the polymer microlattice to leave a metal microlattice, depositing graphitic carbon on the metal microlattice, converting the graphitic carbon to graphene, and removing the metal microlattice.

公开(公告)号：US11908776B2

公开(公告)日：2024-02-20

申请号：US17142598

申请日：2021-01-06

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Sreenivasan Koduri

IPC: H01L23/495 ,  H01L21/48

CPC classification number: H01L23/49513 ,  H01L21/4871 ,  H01L23/49503 ,  H01L23/49548 ,  H01L23/49568 ,  H01L23/49582 ,  H01L2224/32245

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.