公开(公告)号：US20230290880A1

公开(公告)日：2023-09-14

申请号：US17692218

申请日：2022-03-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anupam DUTTA ,  Vvss Satyasuresh CHOPPALLI ,  Rajendran KRISHNASAMY

IPC: H01L29/78 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L29/0611

Abstract: According to various embodiments, there is provided a MOSFET device. The MOSFET device may include a substrate; a first doped region disposed in the substrate; a second doped region disposed in the substrate, wherein the first doped region and the second doped region are laterally adjacent to each other; a third doped region disposed in the first doped region; a fourth doped region disposed in the second doped region; a gate disposed on the substrate, over the first and second doped regions, and between the third and fourth doped regions; and at least one high resistance region embedded in at least the second doped region, wherein the first doped region has a first conductivity type, wherein the second doped region, the third doped region, and the fourth doped region have a second conductivity type, wherein the first conductivity type and the second conductivity type are different.

公开(公告)号：US20230290829A1

公开(公告)日：2023-09-14

申请号：US17804201

申请日：2022-05-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Peter Baars ,  Alexander M. Derrickson ,  Ketankumar Harishbhai Tailor ,  Zhixing Zhao ,  Judson R. Holt

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/735

CPC classification number: H01L29/1004 ,  H01L29/66234 ,  H01L29/735

Abstract: Embodiments of the disclosure provide a bipolar transistor structure having a base with a varying horizontal width and methods to form the same. The bipolar transistor structure includes a first emitter/collector (E/C) layer on an insulator layer. A base layer is over the insulator layer. A spacer between the first E/C layer and the base layer. The base layer includes a lower base region, and the spacer is adjacent to the lower base region and the first E/C layer. An upper base region is on the lower base region and the spacer. A horizontal width of the upper base region is larger than a horizontal width of the lower base region.

公开(公告)号：US20230288321A1

公开(公告)日：2023-09-14

申请号：US17689120

申请日：2022-03-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej J. Pawlak ,  Michal Rakowski

IPC: G01N21/31 ,  G02B6/293

CPC classification number: G01N21/31 ,  G02B6/29343 ,  G02B6/2935

Abstract: Disclosed is a structure (e.g., a lab-on-chip structure) including a substrate, an insulator layer on the substrate, and at least one optical ring resonator. Each ring resonator includes cladding material on the insulator layer and, embedded within the cladding material, a first waveguide core with an input and an output, and second waveguide core(s) (e.g., ring waveguide core(s)) positioned laterally adjacent to the first waveguide core. A reservoir is below the ring resonator within the insulator layer and substrate such that surfaces of the waveguide cores are exposed within the reservoir. During a sensing operation, the waveguide core surfaces contact with fluid within the reservoir and a light signal at the output of the first waveguide core is monitored (e.g., by a sensing circuit, which in some embodiments is also coupled to a reference optical ring resonator) and used, for example, for spectrum-based target identification and, optionally, characterization.

公开(公告)号：US20230282707A1

公开(公告)日：2023-09-07

申请号：US17687941

申请日：2022-03-07

Applicant: GlobalFoundries U.S. Inc.

Inventor： Navneet K. Jain ,  Mahbub Rashed

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/1087 ,  H01L27/1203 ,  H01L29/7838

Abstract: Integrated structures include (among other components) a deep well structure having a first impurity, well rows contacting the deep well structure and having a second impurity, a well contact ring enclosing the well rows within an enclosed area, a transistor layer on the well rows, transistors within the transistor layer, and at least one ring-enclosed contact contacting the deep well structure. The ring-enclosed contact is positioned within the enclosed area. Such structures further include a well contact connection contacting the well contact ring and the ring-enclosed contact.

公开(公告)号：US11749717B2

公开(公告)日：2023-09-05

申请号：US17738179

申请日：2022-05-06

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Uzma Rana ,  Anthony K. Stamper ,  Johnatan A. Kantarovsky ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L29/06 ,  H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/763 ,  H01L29/10

CPC classification number: H01L29/0653 ,  H01L21/763 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823481 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7841

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with an embedded isolation layer in a bulk substrate and methods of manufacture. The structure includes: a bulk substrate; an isolation layer embedded within the bulk substrate and below a top surface of the bulk substrate; a deep trench isolation structure extending through the bulk substrate and contacting the embedded isolation layer; and a gate structure over the top surface of the bulk substrate and vertically spaced away from the embedded isolation layer, the deep trench isolation structure and the embedded isolation layer defining an active area of the gate structure in the bulk substrate.

公开(公告)号：US11740418B2

公开(公告)日：2023-08-29

申请号：US17209416

申请日：2021-03-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas A. Polomoff ,  John J. Ellis-Monaghan ,  Frank G. Kuechenmeister ,  Jae Kyu Cho ,  Michal Rakowski

IPC: G02B6/42 ,  H01L23/00 ,  G02B6/30 ,  G02B6/12

CPC classification number: G02B6/4248 ,  G02B6/30 ,  H01L23/562 ,  G02B2006/12119

Abstract: Embodiments of the disclosure provide a photonic integrated circuit (PIC) structure with a passage for a waveguide through a barrier structure. The PIC structure includes a barrier structure on a substrate, having a first sidewall and a second sidewall opposite the first sidewall. A passage is within the barrier structure, and extends from a first end at the first sidewall of the barrier structure to a second end at the second sidewall of the barrier structure. A shape of the passage includes a reversal segment between the first end and the second end. A waveguide within the passage and extends from the first end to the second end of the barrier structure.

公开(公告)号：US20230268335A1

公开(公告)日：2023-08-24

申请号：US17679655

申请日：2022-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Juhan KIM ,  Sangmoon J. KIM ,  Mahbub RASHED ,  Navneet K. JAIN

IPC: H01L27/02

CPC classification number: H01L27/0207

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cell layouts in semiconductor structures and methods of manufacture. A structure includes: a plurality of abutting cells each of which include transistors with gate structures having diffusion regions; a contact spanning across abutting cells of the plurality of abutting cells and contacting to the diffusion regions of separate cells of the abutting cells; and a continuous active region spanning across the plurality of abutting cells, wherein the continuous active region includes a drain-source abutment with L-shape construct, a source-source abutment with U-shape construct, and a drain-drain abutment with a filler cell located between a drain-drain abutment.

公开(公告)号：US20230261062A1

公开(公告)日：2023-08-17

申请号：US17671879

申请日：2022-02-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Uppili Raghunathan ,  Vibhor Jain ,  Sebastian Ventrone ,  Johnatan Kantarovsky ,  Yves Ngu

IPC: H01L29/40 ,  H01L29/735 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/407 ,  H01L29/735 ,  H01L29/0646 ,  H01L29/423 ,  H01L29/401

Abstract: Structures with an isolation region and fabrication methods for a structure having an isolation region. The structure includes a semiconductor substrate, a first isolation region surrounding a portion of the semiconductor substrate, a device in the portion of the semiconductor substrate, and a second isolation region surrounding the first isolation region and the portion of the semiconductor substrate.

公开(公告)号：US20230260561A1

公开(公告)日：2023-08-17

申请号：US17671652

申请日：2022-02-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

IPC: G11C11/22

CPC classification number: G11C11/223 ,  G11C11/2273 ,  G11C11/2275

Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

公开(公告)号：US11721728B2

公开(公告)日：2023-08-08

申请号：US16777531

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Sipeng Gu ,  Jiehui Shu ,  Halting Wang ,  Yanping Shen

IPC: H01L29/417 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L29/41791 ,  H01L29/7851

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.