公开(公告)号：US12198221B2

公开(公告)日：2025-01-14

申请号：US18436494

申请日：2024-02-08

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Narayan Srinivasa ,  Feng Chen ,  Joydeep Ray ,  Ben J. Ashbaugh ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Balaji Vembu ,  Tsung-Han Lin ,  Kamal Sinha ,  Rajkishore Barik ,  Sara S. Baghsorkhi ,  Justin E. Gottschlich ,  Altug Koker ,  Nadathur Rajagopalan Satish ,  Farshad Akhbari ,  Dukhwan Kim ,  Wenyin Fu ,  Travis T. Schluessler ,  Josh B. Mastronarde ,  Linda L Hurd ,  John H. Feit ,  Jeffery S. Boles ,  Adam T. Lake ,  Karthik Vaidyanathan ,  Devan Burke ,  Subramaniam Maiyuran ,  Abhishek R. Appu

IPC: G06T1/20 ,  G06F8/41 ,  G06F9/455 ,  G06F9/50 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084

Abstract: Embodiments provide mechanisms to facilitate compute operations for deep neural networks. One embodiment comprises a graphics processing unit comprising one or more multiprocessors, at least one of the one or more multiprocessors including a register file to store a plurality of different types of operands and a plurality of processing cores. The plurality of processing cores includes a first set of processing cores of a first type and a second set of processing cores of a second type. The first set of processing cores are associated with a first memory channel and the second set of processing cores are associated with a second memory channel.

公开(公告)号：US12197601B2

公开(公告)日：2025-01-14

申请号：US17560193

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Ren Wang ,  Sameh Gobriel ,  Somnath Paul ,  Yipeng Wang ,  Priya Autee ,  Abhirupa Layek ,  Shaman Narayana ,  Edwin Verplanke ,  Mrittika Ganguli ,  Jr-Shian Tsai ,  Anton Sorokin ,  Suvadeep Banerjee ,  Abhijit Davare ,  Desmond Kirkpatrick ,  Rajesh M. Sankaran ,  Jaykant B. Timbadiya ,  Sriram Kabisthalam Muthukumar ,  Narayan Ranganathan ,  Nalini Murari ,  Brinda Ganesh ,  Nilesh Jain

IPC: G06F15/78 ,  G06F9/50 ,  G06F21/62 ,  G06F21/72

Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

公开(公告)号：US12197357B2

公开(公告)日：2025-01-14

申请号：US17556853

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Robert J. Safranek ,  Robert G. Blankenship ,  Venkatraman Iyer ,  Jeff Willey ,  Robert Beers ,  Darren S. Jue ,  Arvind A. Kumar ,  Debendra Das Sharma ,  Jeffrey C. Swanson ,  Bahaa Fahim ,  Vedaraman Geetha ,  Aaron T. Spink ,  Fulvio Spagna ,  Rahul R. Shah ,  Sitaraman V. Iyer ,  William Harry Nale ,  Abhishek Das ,  Simon P. Johnson ,  Yuvraj S. Dhillon ,  Yen-Cheng Liu ,  Raj K. Ramanujan ,  Robert A. Maddox ,  Herbert H. Hum ,  Ashish Gupta

IPC: G06F13/22 ,  G06F1/3287 ,  G06F8/71 ,  G06F8/77 ,  G06F9/30 ,  G06F9/445 ,  G06F9/46 ,  G06F11/10 ,  G06F12/0806 ,  G06F12/0808 ,  G06F12/0813 ,  G06F12/0815 ,  G06F12/0831 ,  G06F13/40 ,  G06F13/42 ,  H04L9/06 ,  H04L49/15 ,  G06F8/73 ,  H04L12/46 ,  H04L45/74

Abstract: A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.

公开(公告)号：US20250016567A1

公开(公告)日：2025-01-09

申请号：US18793322

申请日：2024-08-02

Applicant: Intel Corporation

Inventor： Markus Dominik Mueck

IPC: H04W12/12 ,  H04B17/24

Abstract: The present disclosure is related to reconfigurable radio equipment and edge computing, and in particular, to technologies for cyber security and radio equipment supporting certain features ensuring protection from fraud, and testing interfaces related to reconfigurable radio equipment. Other embodiments may be described and/or claimed.

公开(公告)号：US20250015974A1

公开(公告)日：2025-01-09

申请号：US18887066

申请日：2024-09-17

Applicant: Intel Corporation

Inventor： Robert VAUGHN ,  John HANSEN

IPC: H04L9/08

Abstract: Provided is a method for detecting an Artificial Intelligence (AI) agent of an application in a network. In this method, the varieties of a plurality of outputs of the application may be determined, where the outputs are respectively corresponding to a plurality of identical inputs provided to the application. Furthermore, the method may detect, based on the varieties of the plurality of outputs, the AI agent of the application, wherein the AI agent comprises an AI model providing AI-based resource information to the application to generate the plurality of outputs.

公开(公告)号：US20250014967A1

公开(公告)日：2025-01-09

申请号：US18893576

申请日：2024-09-23

Applicant: Intel Corporation

Inventor： Kyle Jordan Arrington ,  Prabhakar Subrahmanyam ,  Steven Adam Klein ,  Kelly Porter Lofgreen ,  Joseph Blane Petrini

IPC: H01L23/473 ,  H01L23/40 ,  H01L23/42 ,  H01R12/85 ,  H01R13/52

Abstract: Systems, apparatus, articles of manufacture, and methods to improve thermal dissipation and mechanical loading of integrated circuit packages are disclosed. An example apparatus includes: a socket to receive an integrated circuit package; and a plate to apply a load on the integrated circuit package towards the socket. The plate includes an internal channel to carry a coolant through the plate. The liquid coolant is to facilitate cooling of the integrated circuit package.

公开(公告)号：US20250013420A1

公开(公告)日：2025-01-09

申请号：US18895818

申请日：2024-09-25

Applicant: Intel Corporation

Inventor： Sean J. W. Lawrence

IPC: G06F3/147 ,  G06F3/01

Abstract: Systems and methods for controlling flexible displays are disclosed herein. An example apparatus includes interface circuitry; machine-readable instructions; and at least one processor circuit to at least one of instantiate or execute the machine-readable instructions to determine a distance of a user relative to a display screen based on outputs of a sensor, the sensor in communication with one or more of the at least one processor circuit; determine a curvature radius of the display screen based on the user distance; and cause an actuator to adjust a curvature of the display screen based on the curvature radius.

公开(公告)号：US20250013233A1

公开(公告)日：2025-01-09

申请号：US18891741

申请日：2024-09-20

Applicant: Intel Corporation

Inventor： Igor Tatourian ,  Hassnaa Moustafa ,  David John Zage

IPC: G05D1/00 ,  B25J9/16 ,  B60W30/09

Abstract: Apparatuses, storage media and methods associated with cognitive robot systems, such as ADAS for CAD vehicles, are disclosed herein. In some embodiments, an apparatus includes emotional circuitry to receive stimuli for a robot integrally having the robotic system, process the received stimuli to identify potential adversities, and output information describing the identified potential adversities; and thinking circuitry to receive the information describing the identified potential adversities, process the received information describing the identified potential adversities to determine respective fear levels for the identified potential adversities in view of a current context of the robot, and generate commands to the robot to respond to the identified potential adversities, based at least in part on the determined fear levels for the identified potential adversities. Other embodiments are also described and claimed.

公开(公告)号：US12192464B2

公开(公告)日：2025-01-07

申请号：US18018182

申请日：2020-08-27

Applicant: INTEL CORPORATION

Inventor： Vasily Aristarkhov

IPC: H04N7/12 ,  H04N19/127 ,  H04N19/423 ,  H04N19/436

Abstract: A multi-adapter encoding process where the first adapter is used to execute a look-ahead encoding process while the second adapter is used to execute a main encoding process is provided. The look-ahead encode and main encode can be executed concurrently on the different adapters. Additionally, the first adapter can execute the look-ahead encoding process without feedback from the second adapter, or the main encoding process.

公开(公告)号：US12191871B2

公开(公告)日：2025-01-07

申请号：US17355217

申请日：2021-06-23

Applicant: Intel Corporation

Inventor： Evgeny Shumaker ,  Elan Banin ,  Ofir Degani ,  Gil Horovitz

IPC: H03L7/24 ,  G04F10/00 ,  H03L7/085 ,  H03L7/099

Abstract: A TDC circuit configured to receive a reference clock (REF) signal and a signal derived from a LO; generate a plurality of digital values indicative of a measured phase difference between the signal derived from the LO and the REF signal, wherein each of the plurality of digital values are determined from a unique set of a plurality of sets of TDC measurement component quantization levels; generate a combined series of quantization levels based on a combination of the plurality of sets of TDC measurement component quantization levels; and determine a combined digital value from the combined series of quantization levels and at least one of the plurality of digital values to generate an output of the TDC circuit. The combined series of quantization levels may be generated by summing simultaneously occurring levels of each of the plurality of sets of TDC measurement component quantization levels together.