公开(公告)号：US20150229403A1

公开(公告)日：2015-08-13

申请号：US14179447

申请日：2014-02-12

Applicant: INPHI CORPORATION

Inventor： Hari SHANKAR

IPC: H04B10/516 ,  H04B10/2575

CPC classification number: H04B10/516 ,  H04B10/2575 ,  H04B10/50572 ,  H04B10/50593 ,  H04B10/588

Abstract: The present invention is directed to optical communication systems and methods thereof. In various embodiments, the present invention provides method for linearizing Mach Zehnder modulators by digital pre-compensation and adjusting the gain of the driver and/or the modulation index. The pre-compensation can be implemented as a digital pre-compensation algorithm, which is a part of an adaptive feedback loop. There are other embodiments as well.

Abstract translation: 本发明涉及光通信系统及其方法。 在各种实施例中，本发明提供了通过数字预补偿线性化马赫曾德调制器并调整驱动器的增益和/或调制指数的方法。 预补偿可以实现为数字预补偿算法，其是自适应反馈回路的一部分。 还有其它实施例。

公开(公告)号：US20150121133A1

公开(公告)日：2015-04-30

申请号：US14593257

申请日：2015-01-09

Applicant: INPHI CORPORATION

Inventor： David WANG

IPC: G06F11/10 ,  G06F11/00

CPC classification number: G06F11/1076 ,  G06F11/008 ,  G06F11/1004 ,  G06F11/1016 ,  G06F12/00

Abstract: A buffer integrated circuit device. The device comprising an output driver formed on the substrate member, the output driver having at least a command bus and an address bus. The device has a protocol and parity checking block (“Block”). The device has a table configured in the block. The table is programmable with a plurality of timing parameters. The device has a memory state block coupled to the table and a command history table coupled to the table to process protocol information for all commands that pass through the Block. The buffer integrated circuit device utilizes the protocol checking functionality to prevent failure propagation and enables data protection even in the case of host memory controller failure or system-level failure of any signal or signals on the command, control and address bus from the host memory controller to the buffer integrated device.

Abstract translation: 缓冲器集成电路器件。 所述装置包括形成在所述衬底构件上的输出驱动器，所述输出驱动器至少具有命令总线和地址总线。 该设备具有协议和奇偶校验块（“块”）。 该设备具有在该块中配置的表。 该表可以用多个定时参数来编程。 该设备具有耦合到该表的存储器状态块和耦合到该表的命令历史表，以处理通过该块的所有命令的协议信息。 缓冲器集成电路器件利用协议检查功能来防止故障传播，并且即使在主机存储器控制器故障或者来自主机存储器控制器的命令，控制和地址总线上的任何信号或信号的系统级故障的情况下也能够进行数据保护 到缓冲器集成器件。

公开(公告)号：US20150110501A1

公开(公告)日：2015-04-23

申请号：US14583331

申请日：2014-12-26

Applicant: INPHI CORPORATION

Inventor： Carl POBANZ

IPC: G02F1/225 ,  H04B10/25 ,  H04L7/00

CPC classification number: G02F1/0121 ,  G02F1/0123 ,  G02F1/025 ,  G02F1/225 ,  G02F1/2255 ,  G02F1/2257 ,  G02F2001/0154 ,  G02F2001/212 ,  H04B10/25 ,  H04B10/505 ,  H04L7/0075

Abstract: An optical modulator device directly-coupled to a driver circuit device. The optical modulator device can include a transmission line electrically coupled to an internal VDD, a first electrode electrically coupled to the transmission line, a second electrode electrically coupled to the first electrode and the transmission line. A wave guide can be operably coupled to the first and second electrodes, and a driver circuit device can be directly coupled to the transmission line and the first and second electrodes. This optical modulator and the driver circuit device can be configured without back termination.

Abstract translation: 直接耦合到驱动器电路装置的光调制器装置。 光调制器装置可以包括电耦合到内部VDD的传输线，电耦合到传输线的第一电极，电耦合到第一电极和传输线的第二电极。 波导可以可操作地耦合到第一和第二电极，并且驱动器电路装置可以直接耦合到传输线和第一和第二电极。 该光调制器和驱动器电路装置可以被配置为没有后端接。

公开(公告)号：US09015558B2

公开(公告)日：2015-04-21

申请号：US14228847

申请日：2014-03-28

Applicant: Inphi Corporation

Inventor： David Wang ,  Christopher Haywood

IPC: G11C29/00 ,  G06F11/10 ,  G11C7/10 ,  G11C11/408 ,  G11C29/52 ,  H03M13/15 ,  G11C29/04

CPC classification number: G06F11/1068 ,  G06F11/10 ,  G11C7/1006 ,  G11C11/408 ,  G11C29/52 ,  G11C29/848 ,  G11C2029/0411 ,  H03M13/1515 ,  H03M13/152

Abstract: The present systems include a memory module containing a plurality of RAM chips, typically DRAM, and a memory buffer arranged to buffer data between the DRAM and a host controller. The memory buffer includes an error detection and correction circuit arranged to ensure the integrity of the stored data words. One way in which this may be accomplished is by computing parity bits for each data word and storing them in parallel with each data word. The error detection and correction circuit can be arranged to detect and correct single errors, or multi-errors if the host controller includes its own error detection and correction circuit. Alternatively, the locations of faulty storage cells can be determined and stored in an address match table, which is then used to control multiplexers that direct data around the faulty cells, to redundant DRAM chips in one embodiment or to embedded SRAM in another.

Abstract translation: 本系统包括存储模块，该存储器模块包含多个RAM芯片，通常为DRAM，以及一个存储器缓冲器，用于缓冲DRAM和主机控制器之间的数据。 存储器缓冲器包括错误检测和校正电路，其布置成确保存储的数据字的完整性。 可以实现这一点的一种方式是通过计算每个数据字的奇偶校验位并将它们与每个数据字并行存储。 如果主机控制器包括自己的错误检测和校正电路，则可以将错误检测和校正电路设置为检测和纠正单个错误或多个错误。 或者，可以确定故障存储单元的位置并将其存储在地址匹配表中，该地址匹配表然后被用于控制将故障单元周围的数据引导到冗余DRAM芯片或在另一实施例中的嵌入式SRAM。

公开(公告)号：US08995600B1

公开(公告)日：2015-03-31

申请号：US14452360

申请日：2014-08-05

Applicant: INPHI Corporation

Inventor： Karthik S. Gopalakrishnan ,  Guojun Ren

IPC: H03D3/24 ,  H04L7/033

CPC classification number: H04L7/0331 ,  H03K5/131 ,  H03K5/135 ,  H03L7/08 ,  H03L7/0814 ,  H04L27/04

Abstract: A phase interpolator (PI) is provided to adjust the phase of a clock such that the phase is aligned to an incoming data pattern from a data stream. The data can be captured from a device such as a flip-flop or the like. The present technique uses a PI (digital to phase) and a digital state machine in a feedback loop to set the correct digital code to the PI inputs to achieve an appropriate clock phase. Of course, there can be variations.

公开(公告)号：US08990488B2

公开(公告)日：2015-03-24

申请号：US14228673

申请日：2014-03-28

Applicant: Inphi Corporation

Inventor： Christopher Haywood

IPC: G06F13/00 ,  G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0685 ,  G06F3/0604 ,  G06F3/0659 ,  G06F13/1642 ,  G06F13/1694

Abstract: The present memory system includes a memory buffer having an interface arranged to buffer data and/or command bytes being written to or read from the RAM chips residing on a DIMM by a host controller. The memory buffer further includes at least one additional interface arranged to buffer data and/or command bytes between the host controller or RAM chips and one or more external devices coupled to the at least one additional interface. For example, the memory buffer may include a SATA interface and be arranged to convey data between the host controller or RAM chips and FLASH memory devices coupled to the SATA interface. The additional interfaces may include, for example, a SATA interface, an Ethernet interface, an optical interface, and/or a radio interface.

Abstract translation: 本存储器系统包括存储器缓冲器，其具有被布置为缓冲由主机控制器写入或存储在DIMM上的RAM芯片的数据和/或命令字节的接口。 存储器缓冲器还包括至少一个额外的接口，其布置成在主机控制器或RAM芯片与耦合到至少一个附加接口的一个或多个外部设备之间缓冲数据和/或命令字节。 例如，存储器缓冲器可以包括SATA接口，并且被布置成在主机控制器或RAM芯片与耦合到SATA接口的闪存设备之间传送数据。 附加接口可以包括例如SATA接口，以太网接口，光接口和/或无线电接口。

公开(公告)号：US08964820B2

公开(公告)日：2015-02-24

申请号：US14479121

申请日：2014-09-05

Applicant: Inphi Corporation

Inventor： Parmanand Mishra ,  Michael S. Harwood

IPC: H04B1/38 ,  H04L25/06 ,  H04B3/04

CPC classification number: H04L25/063 ,  H03M9/00 ,  H04B1/38 ,  H04B3/04 ,  H04B3/14

Abstract: The present invention is directed to integrated circuits. In a specific embodiment, high frequency signals from an equalizer are directly connected to a first pair of inputs of a sense amplifier. The sense amplifier also has a second pair of inputs, which can be selectively coupled to output signals from a DAC or high frequency loopback signals. There are other embodiments as well.

Abstract translation: 本发明涉及集成电路。 在具体实施例中，来自均衡器的高频信号直接连接到读出放大器的第一对输入端。 读出放大器还具有第二对输入，其可以选择性地耦合到来自DAC或高频环回信号的输出信号。 还有其它实施例。

公开(公告)号：US20150049539A1

公开(公告)日：2015-02-19

申请号：US14527644

申请日：2014-10-29

Applicant: INPHI CORPORATION

Inventor： David T. WANG

IPC: G11C29/04 ,  G11C11/24

CPC classification number: G11C29/04 ,  G11C11/24 ,  G11C11/40 ,  G11C29/76 ,  G11C29/808 ,  G11C29/846

Abstract: A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells.

Abstract translation: 提供存储器集成电路器件。 该设备包括多个常规地址输入和至少一个为所选模式或未选择模式配置的备用地址输入。 该装置包括多个控制输入，多个数据输入和多个数据输出。 该装置具有多个存储器阵列。 每个存储器阵列包括多个存储单元。 多个存储单元中的每一个耦合到数据输入/输出。 该设备具有包括多个备用存储器单元的存储器单元的备用组。 多个备用存储单元中的每一个都使用地址匹配表进行外部（或内部）可寻址，并配置有备用地址输入; 于是备用地址输入被耦合到地址匹配表以访问备用存储器单元。

公开(公告)号：US20150016493A1

公开(公告)日：2015-01-15

申请号：US14479121

申请日：2014-09-05

Applicant: INPHI CORPORATION

Inventor： Parmanand MISHRA ,  Michael S. HARWOOD

IPC: H04L25/06 ,  H04B3/04 ,  H04B1/38

CPC classification number: H04L25/063 ,  H03M9/00 ,  H04B1/38 ,  H04B3/04 ,  H04B3/14

Abstract: The present invention is directed to integrated circuits. In a specific embodiment, high frequency signals from an equalizer are directly connected to a first pair of inputs of a sense amplifier. The sense amplifier also has a second pair of inputs, which can be selectively coupled to output signals from a DAC or high frequency loopback signals. There are other embodiments as well.

Abstract translation: 本发明涉及集成电路。 在具体实施例中，来自均衡器的高频信号直接连接到读出放大器的第一对输入端。 读出放大器还具有第二对输入，其可以选择性地耦合到来自DAC或高频环回信号的输出信号。 还有其它实施例。

公开(公告)号：US08902638B2

公开(公告)日：2014-12-02

申请号：US13791807

申请日：2013-03-08

Applicant: Inphi Corporation

Inventor： David T. Wang

IPC: G11C29/04 ,  G11C11/24 ,  G11C11/40 ,  G11C29/00

CPC classification number: G11C29/04 ,  G11C11/24 ,  G11C11/40 ,  G11C29/76 ,  G11C29/808 ,  G11C29/846

Abstract: A memory integrated circuit device is provided. The device includes a plurality of regular address inputs and at least one spare address input configured for a selected mode or an unselected mode. The device includes a plurality of control inputs, a plurality of data inputs, and a plurality of data outputs. The device has a plurality of memory arrays. Each of the memory arrays comprises a plurality of memory cells. Each of the plurality of memory cells is coupled to a data input/output. The device has a spare group of memory cells comprising a plurality of spare memory cells. Each of the plurality of spare memory cells is externally (or internally) addressable using the address match table and configured with the spare address input; whereupon the spare address input is coupled to the address match table to access the spare memory cells.

Abstract translation: 提供存储器集成电路器件。 该设备包括多个常规地址输入和至少一个为所选模式或未选择模式配置的备用地址输入。 该装置包括多个控制输入，多个数据输入和多个数据输出。 该装置具有多个存储器阵列。 每个存储器阵列包括多个存储单元。 多个存储单元中的每一个耦合到数据输入/输出。 该设备具有包括多个备用存储器单元的存储器单元的备用组。 多个备用存储单元中的每一个都使用地址匹配表进行外部（或内部）可寻址，并配置有备用地址输入; 于是备用地址输入被耦合到地址匹配表以访问备用存储器单元。