公开(公告)号：US20230223267A1

公开(公告)日：2023-07-13

申请号：US17573466

申请日：2022-01-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul SHARANGPANI ,  Fei ZHOU ,  Raghuveer S. MAKALA ,  Yujin TERASAWA ,  Naoki TAKEGUCHI ,  Kensuke YAMAGUCHI

IPC: H01L21/285 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L27/24 ,  H01L21/768 ,  C23C16/14 ,  C23C16/455

CPC classification number: H01L21/28568 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/11597 ,  H01L27/2481 ,  H01L21/76876 ,  C23C16/14 ,  C23C16/45525 ,  H01L21/76846

Abstract: A method of depositing a metal includes providing a structure a process chamber, and providing a metal fluoride gas and a growth-suppressant gas into the process chamber to deposit the metal over the structure. The metal may comprise a word line or another conductor of a three-dimensional memory device.

公开(公告)号：US11699494B2

公开(公告)日：2023-07-11

申请号：US17340826

申请日：2021-06-07

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Yu-Chung Lien ,  Deepanshu Dutta ,  Huai-yuan Tseng ,  Ravi Kumar

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C2216/16

Abstract: A method for programming a memory block of a non-volatile memory structure, wherein the method provides, during a program verify operation, selecting only a partial segment of memory cells of a memory block for bit scan mode, applying a sensing bias voltage to one or more bit lines of the memory block associated with the selected memory cells, and initiating a bit scan mode of the selected memory cells.

公开(公告)号：US11694755B2

公开(公告)日：2023-07-04

申请号：US17337329

申请日：2021-06-02

Applicant: SanDisk Technologies LLC

Inventor： Hiroyuki Mizukoshi ,  Heguang Li ,  Althaf Rahamathulla ,  Qihan Li

IPC: G11C16/34 ,  G11C29/02 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/3481 ,  G11C16/102 ,  G11C16/26 ,  G11C16/3459 ,  G11C29/021

Abstract: An apparatus includes control circuits configured to connect to a plurality of non-volatile memory cells. The control circuits are configured to abort fine programming of the plurality of non-volatile memory cells at an intermediate stage and read the plurality of non-volatile memory cells at the intermediate stage to obtain first partial data of at least one logical page. The control circuits are configured obtain the at least one logical page of data by combining the first partial data with second partial data of the at least one logical page stored in data latches.

公开(公告)号：US20230209821A1

公开(公告)日：2023-06-29

申请号：US17562888

申请日：2021-12-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masashi Ishida

IPC: H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  G11C16/04 ,  H01L29/06

CPC classification number: H01L27/11524 ,  H01L27/11519 ,  H01L27/11556 ,  G11C16/0483 ,  H01L29/0649

Abstract: A field effect transistor includes a source region embedded in a semiconductor material layer, a drain region embedded in the semiconductor material layer and laterally spaced from the source region by a channel, a gate stack including a gate dielectric and a gate electrode, a shallow trench isolation portion embedded in an upper portion of the semiconductor material layer and contacting the drain region and the gate stack, and a concave drain extension region continuously extending underneath the shallow trench isolation portion from a bottom surface of the gate dielectric to a bottom surface of the drain region.

公开(公告)号：US20230207022A1

公开(公告)日：2023-06-29

申请号：US17562123

申请日：2021-12-27

Applicant: SanDisk Technologies LLC

Inventor： Iris Lu ,  Tai-Yuan Tseng ,  Chia-Kai Chou

IPC: G11C16/26 ,  G11C16/24 ,  G11C16/34 ,  G11C16/04 ,  G11C11/16

CPC classification number: G11C16/26 ,  G11C16/24 ,  G11C16/3459 ,  G11C16/0483 ,  G11C11/1673 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1677 ,  H01L25/0657

Abstract: A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.

公开(公告)号：US20230197172A1

公开(公告)日：2023-06-22

申请号：US17557492

申请日：2021-12-21

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Ken Oowada ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

CPC classification number: G11C16/3454 ,  G11C16/3409 ,  G11C16/102 ,  G11C16/14 ,  G11C16/26 ,  G11C16/08

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells connected to one of a plurality of word lines including an edge word line and a plurality of other data word lines. The memory cells are disposed in memory holes organized in rows grouped in a plurality of strings. The rows include full circle rows and semi-circle rows. A control means is configured to program the memory cells connected to the edge word line and in the semi-circle rows of a first one and a second one of the plurality of strings to a predetermined one of a plurality of data states in a first program operation. The control means then selects both the first one and the second one of the plurality of strings together and programs the memory cells of the full circle rows together in a second program operation.

公开(公告)号：US20230197168A1

公开(公告)日：2023-06-22

申请号：US17549457

申请日：2021-12-13

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Dengtao Zhao ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/28 ,  G11C16/10

CPC classification number: G11C16/28 ,  G11C16/10

Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).

公开(公告)号：US20230186998A1

公开(公告)日：2023-06-15

申请号：US17551640

申请日：2021-12-15

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Abhijith Prakash ,  Shubhajit Mukherjee

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/16 ,  G11C16/32 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/32 ,  G11C16/3404

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells configured to retain a threshold voltage. The memory cells are connected to one of a plurality of word lines and are arranged in strings comprising a plurality of blocks. A control means is coupled to the plurality of word lines and the strings and is configured to periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells. The control means is also configured to relocate data of the one of the plurality of blocks and cause the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.

公开(公告)号：US20230186996A1

公开(公告)日：2023-06-15

申请号：US17549471

申请日：2021-12-13

Applicant: SanDisk Technologies LLC

Inventor： Yi Song ,  Dengtao Zhao ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C7/04

CPC classification number: G11C16/102 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24 ,  G11C7/04

Abstract: A system has been described that performs differential temperature compensation based on a differential between the temperature at time of programming and temperature at time of reading for a set of data. Differential temperature compensation is useful for bulk programming/reading (e.g., many pages of data) and/or programming/reading super pages of data (multiple pages residing on different memory die).

公开(公告)号：US20230186993A1

公开(公告)日：2023-06-15

申请号：US18109466

申请日：2023-02-14

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/10

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/10 ,  H10B41/10

Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.