公开(公告)号：US20240395603A1

公开(公告)日：2024-11-28

申请号：US18694369

申请日：2022-09-20

Applicant: Soitec

Inventor： Gweltaz Gaudin ,  Christophe Maleville ,  Sidoine Odoul ,  Ionut Radu ,  Hugo Biard

IPC: H01L21/763 ,  H01L21/762 ,  H01L29/16

Abstract: A method for manufacturing a composite structure having a layer of monocrystalline silicon carbide on a polycrystalline silicon carbide carrier substrate includes: providing an initial substrate of polycrystalline silicon carbide, having a front face and comprising grains, the average size of which is greater than 0.5 μm; forming a polycrystalline silicon carbide surface layer on the initial substrate to form the carrier substrate, the surface layer including grains having an average size of less than 500 nm and having a thickness of between 50 nm and 50 μm; preparing a free surface of the surface layer of the carrier substrate to obtain a roughness of less than 1 nm RMS; (d) a step of transferring the useful layer onto the carrier substrate, by applying molecular bonding, the surface layer located between the useful layer and the initial substrate. A carrier substrate and a composite structure are formed by the method.

公开(公告)号：US20240392476A1

公开(公告)日：2024-11-28

申请号：US18694796

申请日：2022-10-03

Applicant: Soitec

Inventor： Ionut Radu ,  Hugo Biard ,  Gweltaz Gaudin

IPC: C30B33/06 ,  C30B28/14 ,  C30B29/36 ,  C30B33/02

Abstract: A method of fabricating a composite structure including a thin layer of single-crystal silicon carbide on a polycrystalline SiC carrier substrate includes: forming a polycrystalline SiC layer on a donor substrate, at least a surface portion of which is made of single-crystal SiC; before or after forming the polycrystalline SiC layer, implanting ionic species into the surface portion of the donor substrate, so as to form a plane of weakness delimiting a thin single-crystal SiC layer to be transferred; after the implanting of the ionic species and the forming of the polycrystalline SiC layer, bonding the donor substrate and the polycrystalline SiC carrier substrate, the polycrystalline SiC layer being at the bonding interface; and detaching the donor substrate along the plane of weakness, so as to transfer the polycrystalline SiC layer and the thin single-crystal SiC layer onto the polycrystalline SiC carrier substrate.

公开(公告)号：US20240357937A1

公开(公告)日：2024-10-24

申请号：US18685991

申请日：2022-08-17

Applicant: Soitec

Inventor： Cédric Charles-Alfred ,  Nadia Ben Mohamed

IPC: H10N30/072 ,  H10N30/853

CPC classification number: H10N30/072 ,  H10N30/8536 ,  H10N30/8542 ,  H10N30/8548 ,  H10N30/8554

Abstract: A method for transferring a useful layer to a carrier substrate comprises: a) providing a donor substrate including a donor layer; b) forming an embrittlement area by implanting species in the donor layer and defining therewith a useful layer; c) assembling the carrier substrate with the donor substrate; d) a heat treatment step including a first phase and a second phase, wherein the first phase, having a first duration, is heated to a first temperature and is suitable for maturing defects and preventing a fracture from occurring in the embrittlement area, and wherein the second phase, having a second duration, comprises a bearing at a second temperature, below the first temperature, and is suitable for causing a fracture to occur along the embrittlement area.

公开(公告)号：US20240297011A1

公开(公告)日：2024-09-05

申请号：US18575538

申请日：2022-07-19

Applicant: Soitec

Inventor： Cédric Charles-Alfred

IPC: H01J37/20 ,  H01J37/317 ,  H10N30/04

CPC classification number: H01J37/20 ,  H01J37/3171 ,  H10N30/04

Abstract: A holding device arrangement for use in an implantation process of a piezoelectric substrate comprises a substrate holding device with an elastic and thermo-conductive layer for receiving a piezoelectric substrate, and means for electrically connecting the surface of the elastic and thermo-conductive layer for receiving the piezoelectric substrate to ground potential. A method for implanting a piezoelectric substrate is performed using such holding device arrangement as described above, and an ion implanter may include such a holding device arrangement.

公开(公告)号：US12071706B2

公开(公告)日：2024-08-27

申请号：US17041371

申请日：2019-03-26

Applicant: Soitec

Inventor： Bruno Ghyselen

IPC: C30B33/06 ,  C30B23/02 ,  C30B25/18 ,  C30B29/36 ,  C30B29/40 ,  H01L21/02

CPC classification number: C30B25/18 ,  C30B23/025 ,  C30B29/36 ,  C30B29/403 ,  H01L21/02447 ,  H01L21/0254 ,  H01L21/02598 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02543 ,  H01L21/02546

Abstract: A process for producing a monocrystalline layer of AlN material comprises the transfer of a monocrystalline seed layer of SiC-6H material to a carrier substrate of silicon material, followed by the epitaxial growth of the monocrystalline layer of AlN material.

公开(公告)号：US20240170577A1

公开(公告)日：2024-05-23

申请号：US18551104

申请日：2022-03-17

Applicant: Soitec

Inventor： Ionut Radu ,  Guillaume Besnard ,  Sorin Cristoloveanu

IPC: H01L29/786 ,  H01L21/762

CPC classification number: H01L29/78603 ,  H01L21/76254

Abstract: An NCFET transistor comprises a semiconductor-on-insulator substrate for a field-effect transistor, and the NCFET transistor successively comprises, from its base to its surface: a semiconductor carrier substrate; a single ferroelectric layer, arranged in direct contact with the carrier substrate, which layer is designed to be biased so as to form a negative capacitance; and an active layer of a semiconductor material, which layer is designed to form the channel of the transistor, and is arranged in direct contact with the ferroelectric layer. The NCFET transistor further comprises a channel that is arranged in the active layer, a source and a drain that are arranged in the active layer on either side of the channel, and a gate that is arranged on the channel and is insulated from the channel by a gate dielectric.

公开(公告)号：US11976380B2

公开(公告)日：2024-05-07

申请号：US17816558

申请日：2022-08-01

Applicant: Soitec

Inventor： Bruno Ghyselen

IPC: C30B29/32 ,  C30B23/02 ,  C30B25/18 ,  C30B29/42 ,  H01L21/02 ,  H01L21/762

CPC classification number: C30B29/32 ,  C30B23/025 ,  C30B25/183 ,  C30B29/42 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02645 ,  H01L21/76254

Abstract: A process for producing a monocrystalline layer of GaAs material comprises the transfer of a monocrystalline seed layer of SrTiO3 material to a carrier substrate of silicon material followed by epitaxial growth of a monocrystalline layer of GaAs material.

公开(公告)号：US20240147864A1

公开(公告)日：2024-05-02

申请号：US18403485

申请日：2024-01-03

Applicant: Soitec

Inventor： Didier Landru

IPC: H10N30/073 ,  H03H9/02 ,  H10N30/00 ,  H10N30/50 ,  H10N30/88

CPC classification number: H10N30/073 ,  H03H9/02574 ,  H10N30/10513 ,  H10N30/508 ,  H10N30/88

Abstract: A hybrid structure and a method for manufacturing a hybrid structure comprising an effective layer of piezoelectric material having an effective thickness and disposed on a supporting substrate having a substrate thickness and a thermal expansion coefficient lower than that of the effective layer includes: a) a step of providing a bonded structure comprising a piezoelectric material donor substrate and the supporting substrate, b) a first step of thinning the donor substrate to form a thinned layer having an intermediate thickness and disposed on the supporting substrate, the assembly forming a thinned structure; c) a step of heat treating the thinned structure at an annealing temperature; and d) a second step, after step c), of thinning the thinned layer to form the effective layer. The method also comprises, prior to step b), a step a′) of determining a range of intermediate thicknesses that prevent the thinned structure from being damaged during step c).

公开(公告)号：US11962288B2

公开(公告)日：2024-04-16

申请号：US18248183

申请日：2022-09-15

Applicant: Soitec

Inventor： Eric Michoulier ,  Sylvain Ballandras ,  Thierry LaRoche

IPC: H03H9/64 ,  H03H9/02

CPC classification number: H03H9/643 ,  H03H9/02653

Abstract: A surface elastic wave filter has resonant cavities and comprises a composite substrate formed of a base substrate and a piezoelectric upper layer; at least one input electroacoustic transducer and an output electroacoustic transducer, arranged on the upper layer, and at least one internal reflecting structure, arranged between the input electroacoustic transducer and the output electroacoustic transducer. The internal reflecting structure comprises a first structure comprising at least one reflection grating having a first period and a second structure comprising at least one reflection grating having a second period, the first period being greater than the second period.

公开(公告)号：US20240120240A1

公开(公告)日：2024-04-11

申请号：US18546210

申请日：2022-01-28

Applicant: Soitec

Inventor： YoungPil Kim

IPC: H01L21/66 ,  H01L21/02

CPC classification number: H01L22/26 ,  H01L21/02381 ,  H01L21/02532 ,  H01L22/12 ,  H01L21/0262

Abstract: A setup method for an epitaxy process intended to form a useful layer on a receiving substrate, comprising:



a) selecting a test substrate:

having a thickness less than a usual thickness for a given substrate diameter, and/or
having a low interstitial oxygen concentration, and/or
comprising a SOI stack;


b) fixing initial temperature conditions defining temperatures to be applied to areas of the substrate;
c) forming a useful layer on the test substrate by applying the epitaxy process with the initial temperature conditions; then, measuring slip line defects;
d) fixing new temperature conditions;
e) forming a useful layer on a new test substrate of the same type, by applying the epitaxy process with the new temperature conditions; then, measuring slip line defects; and
f) comparing the quantity of slip line defects measured on the test structures and choosing the temperature conditions generating the fewest slip line defects.