Abstract:
A plasma reactor includes a chamber body having an interior space that provides a plasma chamber, a gas distribution port to deliver a processing gas to the plasma chamber, a workpiece support to hold a workpiece, an antenna array comprising a plurality of monopole antennas extending partially into the plasma chamber, and an AC power source to supply a first AC power to the plurality of monopole antennas. The plurality of monopole antennas are divided into a plurality of groups of monopole antennas, and the AC power source is configured to generate AC power on a plurality of power supply lines at a plurality of different phases, and different groups of monopole antennas are coupled to different power supply lines.
Abstract:
Embodiments described herein relate to apparatus and methods for processing a substrate. In one embodiment, a cluster tool apparatus is provided having a transfer chamber and a pre-clean chamber, a self-assembled monolayer (SAM) deposition chamber, an atomic layer deposition (ALD) chamber, and a post-processing chamber disposed about the transfer chamber. A substrate may be processed by the cluster tool and transferred between the pre-clean chamber, the SAM deposition chamber, the ALD chamber, and the post-processing chamber. Transfer of the substrate between each of the chambers may be facilitated by the transfer chamber which houses a transfer robot.
Abstract:
Embodiments of substrate transfer chambers are provided herein. In some embodiments, a substrate transfer chamber includes a body having an interior volume, wherein a bottom portion of the body includes a first opening; an adapter plate coupled to the bottom portion of the body to couple the substrate transfer chamber to a load lock chamber of a substrate processing system; wherein the adapter plate includes a second opening aligned with the first opening to fluidly couple the interior volume with an inner volume of the load lock chamber; a cassette support disposed in the interior volume to support a substrate cassette; and a lift actuator coupled to the cassette support to lower or raise the substrate cassette into or out of the load lock chamber.
Abstract:
Embodiments method and apparatus for transferring a substrate are provided herein. In some embodiments, a substrate cassette includes a body having an upper portion and a lower portion, the upper portion and the lower portion defining an interior volume when the upper portion is coupled to the lower portion; a locking mechanism moveable between a locked position, in which the upper and lower portions are coupled, and an unlocked position, in which the lower portion can be separated from the upper portion; and a load distribution plate coupled to an upper surface of the upper portion along an edge of the upper portion to distribute a load applied to the load distribution plate.
Abstract:
Provided are methods for etching films comprising transition metals which help to minimize higher etch rates at the grain boundaries of polycrystalline materials. Certain methods pertain to amorphization of the polycrystalline material, other pertain to plasma treatments, and yet other pertain to the use of small doses of halide transfer agents in the etch process.
Abstract:
A processed wafer is described that may be used as a workpiece carrier in semiconductor and mechanical processing. In some examples, the workpiece carrier includes a substrate, an electrode formed on the substrate to carry an electric charge to grip a workpiece, a through hole through the substrate and connected to the electrode, and a dielectric layer over the substrate to isolate the electrode from the workpiece.
Abstract:
Implementations described herein generally relate to methods of selective deposition of metal silicides. More specifically, implementations described herein generally relate to methods of forming nickel silicide nanowires for semiconductor applications. In one implementation, a method of processing a substrate is provided. The method comprises forming a silicon-containing layer on a surface of a substrate, forming a metal-containing layer comprising a transition metal on the silicon-containing layer, forming a confinement layer on exposed surfaces of the metal-containing layer and annealing the substrate at a temperature of less than 400 degrees Celsius to form a metal silicide layer from the silicon-containing layer and the metal-containing layer, wherein the confinement layer inhibits formation of metal-rich metal silicide phases.
Abstract:
Embodiments described herein relate to methods for forming flowable chemical vapor deposition (FCVD) films suitable for high aspect ratio gap fill applications. Various process flows described include ion implantation processes utilized to treat a deposited FCVD film to improve dielectric film density and material composition. Ion implantation processes, curing processes, and annealing processes may be utilized in various sequence combinations to form dielectric films having improved densities at temperatures within the thermal budget of device materials. Improved film quality characteristics include reduced film stress and reduced film shrinkage when compared to conventional FCVD film formation processes.
Abstract:
Embodiments of the disclosure provide apparatus and methods for localized stress modulation for overlay and edge placement error (EPE) using electron or ion implantation. In one embodiment, a process for correcting overlay error on a substrate generally includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining doping parameters to correct overlay error or substrate distortion based on the overlay error map, and providing a doping recipe to a doping apparatus based on the doping parameters determined to correct substrate distortion or overlay error. Embodiments may also provide performing a doping treatment process on the substrate using the determined doping repair recipe, for example, by comparing the overlay error map or substrate distortion with a database library stored in a computing system.
Abstract:
Methods for forming air gaps in an interconnection structure with desired materials formed on different locations of the interconnection structure using an ion implantation process to define an etching boundary followed by an etching process for semiconductor devices are provided. In one embodiment, a method for forming air gaps in an interconnection structure on a substrate, the method includes implanting ions in a first region of an insulating material disposed on a substrate, leaving a second region without implanted ions, the second region having a first surface interfaced with the first region and a second surface interfaced with the substrate, and performing an etching process to selectively etch the second region away from the substrate, forming an air gap between the first region and the substrate.