公开(公告)号：US20180033863A1

公开(公告)日：2018-02-01

申请号：US15225152

申请日：2016-08-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L29/49 ,  H01L21/768 ,  H01L29/40 ,  H01L23/535 ,  H01L29/06

CPC classification number: H01L29/4991 ,  H01L21/764 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/0653 ,  H01L29/401 ,  H01L29/66795 ,  H01L29/785

Abstract: One illustrative method disclosed herein includes, among other things, forming a gate structure above an active region and an isolation region, wherein the gate structure comprises a gate, a first gate cap layer and a first sidewall spacer, removing portions of the first gate cap layer and the first sidewall spacer that are positioned above the active region, while leaving portions of the first gate cap layer and the first sidewall spacer positioned above the isolation region in place, wherein a plurality of spacer cavities are defined adjacent the gate, and forming a replacement air-gap spacer in each of the spacer cavities adjacent the gate and a replacement gate cap layer above the gate, wherein the replacement air-gap spacer comprises an air gap.

公开(公告)号：US09847418B1

公开(公告)日：2017-12-19

申请号：US15219917

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kwan-Yong Lim ,  Min Gyu Sung ,  Chanro Park

IPC: H01L21/33 ,  H01L21/20 ,  H01L21/36 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method includes forming a fin on a substrate. A first liner is formed on the fin. A first dielectric layer is formed above the first liner. A patterned hard mask is formed above the first dielectric layer and has a fin cut opening defined therein. Portions of the first dielectric layer and the first liner disposed below the fin cut opening are removed to expose a portion of the fin. The patterned hard mask layer is removed. The exposed portion of the fin is oxidized to define a diffusion break in the fin.

公开(公告)号：US20170316985A1

公开(公告)日：2017-11-02

申请号：US15647453

申请日：2017-07-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Ruilong Xie ,  Hoon Kim

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L27/0924

Abstract: An integrated circuit product includes an NFET FinFET device having a first fin that is made entirely of a first semiconductor material and a PFET FinFET device that includes a second fin having an upper portion and a lower portion, wherein the lower portion is made of the first semiconductor material and the upper portion is made of a second semiconductor material that is different from the first semiconductor material. A silicon nitride liner is positioned on and in contact with the lower portion of the second fin, wherein the silicon nitride liner is not present on or adjacent to the upper portion of the second fin or on or adjacent to any portion of the first fin.

公开(公告)号：US20170287780A1

公开(公告)日：2017-10-05

申请号：US15089834

申请日：2016-04-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Ruilong Xie ,  Hoon Kim ,  Min Gyu Sung

IPC: H01L21/768 ,  H01L21/28 ,  H01L23/535 ,  H01L27/092 ,  H01L29/49 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L21/76897 ,  H01L21/28088 ,  H01L21/76805 ,  H01L21/76834 ,  H01L21/76883 ,  H01L21/823456 ,  H01L21/823475 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/823871 ,  H01L23/535 ,  H01L27/0924 ,  H01L29/4966 ,  H01L29/66545

Abstract: One method disclosed includes, among other things, forming a first plurality of gate cavities in a first dielectric layer. A work function material layer is formed in the first plurality of gate cavities. A first conductive material is formed in at least a subset of the first plurality of gate cavities above the work function material layer to define a first plurality of gate structures. A first contact recess is formed in the first dielectric layer between two of the first plurality of gate structures. A second conductive material is formed in the first contact recess. The work function material layer is recessed selectively to the first and second conductive materials to define a plurality of cap recesses. A cap layer is formed in the plurality of cap recesses.

公开(公告)号：US09780197B1

公开(公告)日：2017-10-03

申请号：US15378596

申请日：2016-12-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Min Gyu Sung ,  Chanro Park ,  Hoon Kim

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L29/66666 ,  H01L21/28088 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66553

Abstract: Methods for making a vertical transistor and controlling channel length. A fin is formed over a semiconductor substrate. A bottom source/drain region is formed below the fin. A bottom spacer is formed above the source/drain region. A first sacrificial layer is formed around the fin. A second sacrificial layer is formed around the first sacrificial layer. A portion of the first sacrificial layer is removed to create a recess between sidewalls of the second sacrificial layer. A nitride material is deposited into the recess. The second sacrificial layer and remaining portions of the first sacrificial layer are removed. A dielectric layer is deposited on the nitride material and exposed portions of the fin. A gate electrode is formed over sidewalls of the fin.

公开(公告)号：US09741623B2

公开(公告)日：2017-08-22

申请号：US14828652

申请日：2015-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Ruilong Xie ,  Hoon Kim

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L27/0924

Abstract: One illustrative method disclosed herein includes, among other things, performing a first trench etching process to define an upper portion of a first fin for an NFET device and an upper portion of a second fin for a PFET device, performing a first conformal deposition process to form a conformal etch stop layer around the upper portion of both the first and second fins, with the NFET device masked, performing a second trench etching process to define a lower portion of the second fin, and performing a second conformal deposition process to form a conformal protection layer adjacent the upper portion of the second fin and on sidewalls of the lower portion of the second fin.

公开(公告)号：US09735063B2

公开(公告)日：2017-08-15

申请号：US14830245

申请日：2015-08-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chanro Park ,  Min Gyu Sung ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L21/823821 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/31056 ,  H01L21/31116 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/66795

Abstract: A method includes providing a substrate having a first and a second plurality of fins with a first at least one dielectric material disposed thereon, removing upper portions of the first dielectric material to expose upper portions of the first and the second plurality of fins, removing the first dielectric material from the lower portions of the second plurality of fins to expose lower portions of the second plurality of fins, depositing a second at least one dielectric material on at least the upper and the lower exposed portions of the second plurality of fins and on the upper exposed portions of first plurality of fins, removing the second dielectric material to expose upper portions of the first and the second plurality of fins, and wherein the first dielectric material is different from the second dielectric material. The resulting structure may be operable for use as nFETs and pFETs.

公开(公告)号：US09691664B1

公开(公告)日：2017-06-27

申请号：US15170126

申请日：2016-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Hoon Kim ,  Ruilong Xie

IPC: H01L21/00 ,  H01L21/84 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L27/088 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L21/823431 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02238 ,  H01L21/31111 ,  H01L21/823462 ,  H01L21/845 ,  H01L27/0886 ,  H01L29/42364 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a thick oxide layer over fins for EG devices and a thinner oxide layer over fins for SG devices on the same substrate and the resulting device are provided. Embodiments include forming a first set of fins over a first portion of a Si substrate; forming a second set of fins over a second portion of the Si substrate spaced from the first portion; forming an iRAD SiO2 layer over the first and second sets of fins; forming a polysilicon layer over the iRAD SiO2 layer over the first set of fins; forming a radical SiO2 layer over the iRAD SiO2 layer over the second set of fins and over the polysilicon layer; forming a mask over the radical SiO2 layer over the second set of fins; removing the polysilicon layer; and removing the mask and the iRAD SiO2 layer from the first set of fins.

公开(公告)号：US20170053835A1

公开(公告)日：2017-02-23

申请号：US14828652

申请日：2015-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min Gyu Sung ,  Chanro Park ,  Ruilong Xie ,  Hoon Kim

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/823821 ,  H01L21/823807 ,  H01L27/0924

Abstract: One illustrative method disclosed herein includes, among other things, performing a first trench etching process to define an upper portion of a first fin for an NFET device and an upper portion of a second fin for a PFET device, performing a first conformal deposition process to form a conformal etch stop layer around the upper portion of both the first and second fins, with the NFET device masked, performing a second trench etching process to define a lower portion of the second fin, and performing a second conformal deposition process to form a conformal protection layer adjacent the upper portion of the second fin and on sidewalls of the lower portion of the second fin.

Abstract translation: 本文中公开的一种说明性方法包括执行第一沟槽蚀刻工艺以限定NFET器件的第一鳍片的上部分和用于PFET器件的第二鳍片的上部，执行第一共形沉积工艺 在所述第一和第二鳍片的上部周围形成保形蚀刻停止层，其中所述NFET器件被掩蔽，执行第二沟槽蚀刻工艺以限定所述第二鳍片的下部分，以及执行第二共形沉积工艺以形成 保形层邻近第二鳍片的上部并且在第二鳍片的下部的侧壁上。

公开(公告)号：US09536793B1

公开(公告)日：2017-01-03

申请号：US15135917

申请日：2016-04-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Kwan-Yong Lim ,  Steven John Bentley ,  Chanro Park

IPC: H01L29/786 ,  H01L21/8238

CPC classification number: H01L21/823828 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823885

Abstract: Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed. Embodiments include providing a substrate including adjacent transistor regions; forming adjacent and spaced fin-structures each including hardmask over a fin and over a different transistor region; forming a gate-dielectric and metal-spacer consecutively on each side of each fin-structure; forming a liner on all exposed surfaces of the hardmask, gate-dielectrics, and metal-spacers and the substrate; forming an ILD filling spaces between the fin-structures and coplanar with an upper surface of the liner; removing the liner over the fin-structures; removing the hardmask and recessing the liner, the gate-dielectrics and metal-spacers of each fin-structure creating cavities in the ILD; forming a low-k spacer on sidewalls of and over the metal-spacers and liners in each cavity; forming a top S/D structure over the gate-dielectric and fin in each cavity; and forming a top S/D contact over each top S/D structure.

Abstract translation: 公开了使用栅极 - 间隔物凹槽的自对准栅极 - 第一VFET和所得到的器件的方法。 实施例包括提供包括相邻晶体管区域的衬底; 形成相邻和间隔的翅片结构，每个翅片结构包括翅片上的硬掩模和不同的晶体管区域上的硬掩模; 在每个翅片结构的每一侧上连续形成栅电介质和金属间隔物; 在硬掩模，栅极 - 电介质和金属间隔物和基底的所有暴露表面上形成衬垫; 在翅片结构之间形成ILD填充空间并与衬套的上表面共面; 将衬垫移出翅片结构; 去除硬掩模并使衬垫凹陷，每个鳍结构的栅电介质和金属间隔件在ILD中产生空腔; 在每个腔中的金属间隔件和衬垫的侧壁上形成低k间隔物; 在每个腔中的栅电介质和鳍上形成顶部S / D结构; 并且在每个顶部S / D结构上形成顶部S / D接触。