摘要:
A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要:
On the occasion of the aligning process to transfer a predetermined pattern to a semiconductor wafer by irradiating a photoresist on the semiconductor wafer with an aligning laser beam of the modified lighting via a photomask MK, the photomask MK allocating, to provide periodicity, the main apertures to transfer the predetermined pattern as the apertures formed by removing a part of the half-tone film on the mask substrate and the auxiliary apertures not resolved on the semiconductor wafer as the apertures formed by removing a part of the half-tone film is used to improve the resolution of the pattern.
摘要:
A process of producing a semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step. The device is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
摘要:
A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.
摘要:
A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.
摘要:
A semiconductor device has a gate dielectric film formed of zirconium oxide or hafnium oxide as a chief material and a gate electrode film in contact with the gate dielectric film on one principal surface side of a silicon substrate. The gate dielectric film contains an addition element to prevent diffusion of oxygen.
摘要:
A silicon oxide film 2 which is exposed from a side wall of a groove 4a is etched to displace the silicon oxide film 2 backward toward an active region. The displacement amount is set to be equal to or more than a film thickness (Tr) of a silicon oxide film 5 to be formed on an inner wall of the groove 4a in a later thermal oxidation step and equal to or less than twice the film thickness (Tr) thereof. A shoulder portion of the groove 4a can be rounded by a low-temperature heat treatment at 1000.degree. C. or less, by controlling a heat treatment period such that the film thickness (Tr) of the silicon oxide film 5 is more than the film thickness (Tp) of the silicon oxide film 2 and equal to or less than three times the film thickness (Tr) thereof (Tp
摘要:
A semiconductor device comprises a silicon substrate, an electrical wiring metal, an insulating film formed on the silicon substrate, a plurality of contact holes formed in the insulating film for connecting the silicon substrate and the electrical wiring metal to each other, and a titanium silicide film formed in the contact holes. The thickness of the titanium silicide film is 10 nm to 120 nm or, preferably, 20 nm to 84 nm. Semiconductor regions and the electrical wiring metal are connected to each other through the titanium silicide film.
摘要:
A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacitor. The capacitor is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using a structure with decreased resistance such as silicided structure. In addition, there are made common the processing for lowering the resistance of the gate electrode of the transfer MISFETs and the processing for forming the local wiring lines.