公开(公告)号：US20160293602A1

公开(公告)日：2016-10-06

申请号：US14677404

申请日：2015-04-02

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John Hongguang Zhang

IPC: H01L27/098 ,  H01L29/808 ,  H01L21/283 ,  H01L29/417 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/66893 ,  H01L21/283 ,  H01L27/098 ,  H01L29/0657 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41791 ,  H01L29/66909 ,  H01L29/7832 ,  H01L29/8083

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.

Abstract translation: 垂直结型场效应晶体管（JFET）由包括掺杂有第一导电型掺杂剂的半导体衬底内的源极区域的半导体衬底支撑。 掺杂有第一导电型掺杂剂的半导体材料的鳍具有与源极区域接触的第一端，并且还包括第二端和第二端之间的侧壁。 漏极区域由从鳍片的第二端生长并掺杂有第一导电型掺杂剂的第一外延材料形成。 栅极结构由从鳍的侧壁生长并掺杂有第二导电型掺杂剂的第二外延材料形成。

公开(公告)号：US09460971B2

公开(公告)日：2016-10-04

申请号：US14955801

申请日：2015-12-01

Applicant: STMICROELECTRONICS, INC. ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Nicolas Loubet ,  Sylvain Maitrejean ,  Romain Wacquez

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L21/265 ,  H01L21/324 ,  H01L21/266 ,  H01L21/306 ,  H01L21/02 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/845 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/26506 ,  H01L21/266 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/324 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/7849

Abstract: Methods and structures for forming localized, differently-strained regions in a semiconductor layer on a substrate are described. An initial, unstrained, semiconductor-on-insulator substrate may be processed to form the differently-strained regions in the original semiconductor layer. The differently-strained regions may have opposite types of strain. The strains in the different regions may be formed independently.

公开(公告)号：US20160260742A1

公开(公告)日：2016-09-08

申请号：US15156506

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil JACOB ,  Kangguo CHENG ,  Bruce DORIS ,  Nicolas LOUBET ,  Prasanna KHARE ,  Rama DIVAKARUNI

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/308 ,  H01L21/02 ,  H01L21/84 ,  H01L21/306

CPC classification number: H01L27/1211 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/02614 ,  H01L21/0262 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract translation: 提供了由这些方法形成的方法和半导体结构，其有助于制造半导体鳍结构。 所述方法包括例如：提供具有在衬底上延伸的至少一个半导体鳍片的晶片; 将所述半导体鳍片的一部分转换成隔离层，所述隔离层将所述半导体鳍片的半导体层与所述衬底分离; 并且在半导体鳍片的第一鳍片区域中形成第一结构类型的翅片装置，并且在半导体鳍片的第二鳍片区域中形成第二结构类型的鳍片装置（ s），其中第一架构类型和第二架构类型是不同的fin设备架构。

公开(公告)号：US20160255017A1

公开(公告)日：2016-09-01

申请号：US15132521

申请日：2016-04-19

Applicant: STMicroelectronics, Inc.

Inventor： Mahesh Chowdhary ,  Sankalp Dayal

IPC: H04L12/933 ,  H04W4/02

CPC classification number: H04W4/026 ,  H04W4/027 ,  H04W88/02

Abstract: Disclosed herein is a sensor chip including at least one sensing device and a control circuit. The control circuit is configured to receive configuration data as input, and acquire data from the at least one sensing device in accordance with the configuration data. The control circuit classifies a context of the at least one sensing device relative to its surroundings based on analysis of the acquired data in accordance with the configuration data.

Abstract translation: 本文公开了包括至少一个感测装置和控制电路的传感器芯片。 控制电路被配置为接收配置数据作为输入，并且根据配置数据从至少一个感测装置获取数据。 控制电路根据配置数据对所获取的数据的分析，对至少一个感测装置的上下文相对于其周围进行分类。

公开(公告)号：US20160252542A1

公开(公告)日：2016-09-01

申请号：US14749118

申请日：2015-06-24

Applicant: STMicroelectronics, Inc.

Inventor： Mahesh Chowdhary ,  Sankalp Dayal

IPC: G01P1/07 ,  G01P15/00 ,  G01C19/32 ,  G01P1/02

CPC classification number: G01C19/32 ,  G01C19/5776 ,  G01P15/18

Abstract: An electronic device includes a printed circuit board (PCB) having at least one conductive trace thereon. A system on chip (SoC) is mounted on the PCB and electrically coupled to the conductive trace. A sensor chip is mounted on the PCB in a spaced apart relation with the SoC and electrically coupled to the conductive trace such that the sensor chip and SoC are electrically coupled. The sensor chip includes an accelerometer and/or a gyroscope, and a control circuit. The control circuit is configured to receive configuration data as input, acquire data from the accelerometer and/or the gyroscope. The control circuit is also configured to process the data so as to generate a context of the electronic device relative to its surroundings, the processing being performed in using a processing technique operating in accordance with the configuration data, and output the context.

Abstract translation: 电子设备包括其上具有至少一个导电迹线的印刷电路板（PCB）。 片上系统（SoC）安装在PCB上并与导电迹线电耦合。 传感器芯片以与SoC间隔的关系安装在PCB上，并电耦合到导电迹线，使得传感器芯片和SoC电耦合。 传感器芯片包括加速度计和/或陀螺仪，以及控制电路。 控制电路被配置为接收配置数据作为输入，从加速度计和/或陀螺仪获取数据。 控制电路还被配置为处理数据以便相对于其周围环境生成电子设备的上下文，该处理是使用根据配置数据操作的处理技术来执行的，并输出上下文。

公开(公告)号：US09419651B2

公开(公告)日：2016-08-16

申请号：US12651386

申请日：2009-12-31

Applicant: Razmik Karabed ,  Hakan C. Ozdemir ,  Vincent Brendan Ashe ,  Richard Barndt

Inventor： Razmik Karabed ,  Hakan C. Ozdemir ,  Vincent Brendan Ashe ,  Richard Barndt

IPC: H03M13/15 ,  G11B20/18 ,  H03M13/37 ,  H03M13/45

CPC classification number: H03M13/1515 ,  G11B20/1833 ,  G11B2020/1836 ,  G11B2220/2516 ,  H03M13/373 ,  H03M13/451

Abstract: A system and method for correcting errors in an ECC block using soft-decision data. In an embodiment, a soft-decision ECC decoding method, uses “soft” data indicative of how reliable bits of data are when read out. Such a method may use an update module for receiving and manipulating the soft-decision data and iteratively change bits or groups of bits based upon an ordering of the reliability factors. Then a calculator module may determine the total number of errors still remaining after each iteration. Determining just the total number of errors instead of the actual locations is far less computationally intensive, and therefore, many combination of potential flip-bit combination may be analyzed quickly to determine if any combination might reduce the total number of errors enough to be handled by the conventional hard-decision ECC decoding method.

Abstract translation: 一种用于使用软判决数据来校正ECC块中的错误的系统和方法。 在一个实施例中，软判决ECC解码方法使用指示数据可靠位读出时的“软”数据。 这种方法可以使用更新模块来接收和操纵软判决数据，并且基于可靠性因素的排序迭代地改变比特或比特组。 然后，计算器模块可以确定在每次迭代之后仍然存在的错误的总数。 仅确定总错误数量而不是实际位置的计算密集程度远低于计算密集度，因此可以快速分析潜在的翻转比特组合的许多组合，以确定是否有任何组合可能会减少足够数量的错误，以便由 常规的硬判决ECC解码方法。

公开(公告)号：US09412928B2

公开(公告)日：2016-08-09

申请号：US13797072

申请日：2013-03-12

Applicant: STMicroelectronics, Inc.

Inventor： William Donley

IPC: H01L35/32 ,  H01L35/28 ,  B32B38/06 ,  B32B38/10

CPC classification number: H01L35/32 ,  B32B38/06 ,  B32B38/10 ,  B32B2310/024 ,  B32B2457/00 ,  H01L35/28 ,  Y10T156/10

Abstract: A thermoelectric device includes a plurality of thin-film thermoelectric elements. Each thin-film thermoelectric element is a Seebeck-Peltier device. The thin-film thermoelectric elements are electrically coupled in parallel with each other. The thermoelectric device may be fabricated using conventional semiconductor processing technologies and may be a thin-film type device.

公开(公告)号：US09412820B2

公开(公告)日：2016-08-09

申请号：US14456272

申请日：2014-08-11

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Tenko Yamashita ,  Chun-chen Yeh ,  Veeraraghavan S. Basker

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/66 ,  H01L29/786 ,  H01L29/08

CPC classification number: H01L29/1037 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/78603 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

Abstract: A method for making a semiconductor device may include forming a dummy gate above a semiconductor layer on an insulating layer, forming sidewall spacers above the semiconductor layer and on opposing sides of the dummy gate, forming source and drain regions on opposing sides of the sidewall spacers, and removing the dummy gate and underlying portions of the semiconductor layer between the sidewall spacers to provide a thinned channel region having a thickness less than a remainder of the semiconductor layer outside the thinned channel region. The method may further include forming a replacement gate stack over the thinned channel region and between the sidewall spacers and having a lower portion extending below a level of adjacent bottom portions of the sidewall spacers.

Abstract translation: 制造半导体器件的方法可以包括在绝缘层上形成半导体层之上的虚拟栅极，在半导体层上方形成侧壁间隔，在虚设栅极的相对侧上，在侧壁间隔物的相对侧上形成源极和漏极区域 并且在侧壁间隔物之间​​移除半导体层的虚拟栅极和下面的部分，以提供厚度小于稀薄沟道区域外的半导体层的剩余部分的薄化沟道区域。 该方法还可以包括在稀疏的沟道区域和侧壁间隔物之间​​形成替代栅极堆叠，并且具有在侧壁间隔物的相邻底部的水平面下方延伸的下部。

公开(公告)号：US09409394B2

公开(公告)日：2016-08-09

申请号：US13906466

申请日：2013-05-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Kenneth J. Stewart

IPC: B41J2/16 ,  B41J2/14

CPC classification number: B41J2/1433 ,  B41J2/16 ,  B41J2/1635 ,  B41J2202/20

Abstract: A method of making an inkjet print head may include forming, by sawing with a rotary saw blade, continuous slotted recesses in a first surface of a wafer. The continuous slotted recesses may be arranged in parallel, spaced apart relation, and each continuous slotted recess may extend continuously across the first surface. The method may further include forming discontinuous slotted recesses in a second surface of the wafer to be aligned and coupled in communication with the continuous slotted recesses to define alternating through-wafer channels and slotted recess portions. The method may further include selectively filling the residual slotted recess portions to define through-wafer ink channels.

Abstract translation: 制造喷墨打印头的方法可以包括通过用旋转锯片锯切在晶片的第一表面中形成连续的狭槽。 连续的开槽凹槽可以平行布置，间隔开的关系，并且每个连续的开槽凹槽可以连续延伸穿过第一表面。 该方法可以进一步包括在晶片的第二表面中形成不连续的开槽的凹槽，以与待连接的开槽的凹槽对准和耦合，以限定交替的晶片通道和开槽凹部。 该方法还可以包括选择性地填充剩余的开槽凹部以限定贯穿晶片墨水通道。

公开(公告)号：US09406783B2

公开(公告)日：2016-08-02

申请号：US14788737

申请日：2015-06-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/16 ,  H01L29/10 ,  H01L29/165

CPC classification number: H01L27/0924 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed using two epitaxial layers of different lattice constants that are grown over a bulk substrate. A first thin, strained, epitaxial layer may be cut to form strain-relieved base structures for fins. The base structures may be constrained in a strained-relieved state. Fin structures may be epitaxially grown in a second layer over the base structures. The constrained base structures can cause higher amounts of strain to form in the epitaxially-grown fins than would occur for non-constrained base structures.