公开(公告)号：US09035319B2

公开(公告)日：2015-05-19

申请号：US13967923

申请日：2013-08-15

申请人： Kyungpook National University Industry-Academic Cooperation Foundation

发明人： Jung-hee Lee ,  Ki-sik Im ,  Dong-seok Kim ,  Hee-sung Kang ,  Dong-hyeok Son

IPC分类号： H01L29/15 ,  H01L31/0256 ,  H01L21/20 ,  H01L21/36 ,  H01L29/20 ,  H01L21/02 ,  H01L29/739 ,  H01L29/78

CPC分类号： H01L29/2003 ,  H01L21/02365 ,  H01L29/7391 ,  H01L29/785

摘要： The present disclosure relates to nitride semiconductor and a fabricating method thereof, and a nitride semiconductor according to an exemplary embodiment of the present disclosure includes a nitride based first and second electrode placed with a distance on a substrate, a nitride based channel layer which connects the first and second electrode, an insulating layer which covers the channel layer, and a third electrode which is formed to cover the insulating layer on the insulating layer.

摘要翻译： 本公开涉及氮化物半导体及其制造方法，根据本公开的示例性实施方案的氮化物半导体包括在衬底上放置一定距离的基于氮化物的第一和第二电极，将氮化物基沟道层连接 第一和第二电极，覆盖沟道层的绝缘层和形成为覆盖绝缘层上的绝缘层的第三电极。

公开(公告)号：US20150064894A1

公开(公告)日：2015-03-05

申请号：US14542197

申请日：2014-11-14

申请人： SK hynix Inc.

发明人： Min Gyu KOO

IPC分类号： H01L27/115

CPC分类号： H01L27/11524 ,  H01L21/02365 ,  H01L21/28273 ,  H01L27/11539 ,  H01L27/1157 ,  H01L29/788 ,  H01L29/7881

摘要： The semiconductor device includes a semiconductor substrate having a first active area defined by a first isolation layer; a gate insulating layer formed on the semiconductor substrate; a first conductive layer formed on the gate insulating layer; a dielectric layer formed on the first conductive layer; at least one first contact hole passing through the dielectric layer; a second conductive layer, formed on the dielectric layer, the second conductive layer filling the at least one first contact hole to contact the first conductive layer; and at least one first contact plug connected to the second conductive layer in the first active area, wherein the at least one first contact plug is offset from the at least one first contact hole to overlap the dielectric layer.

摘要翻译： 半导体器件包括具有由第一隔离层限定的第一有源区的半导体衬底; 形成在半导体衬底上的栅极绝缘层; 形成在所述栅绝缘层上的第一导电层; 形成在所述第一导电层上的电介质层; 至少一个穿过介电层的第一接触孔; 形成在所述电介质层上的第二导电层，所述第二导电层填充所述至少一个第一接触孔以接触所述第一导电层; 以及至少一个第一接触插塞，其连接到所述第一有源区域中的所述第二导电层，其中所述至少一个第一接触插塞从所述至少一个第一接触孔偏移以与所述介电层重叠。

公开(公告)号：US20150035019A1

公开(公告)日：2015-02-05

申请号：US13956398

申请日：2013-08-01

申请人： QUALCOMM Incorporated

发明人： Stanley Seungchul Song ,  Zhongze Wang ,  Choh fei Yeap

IPC分类号： H01L21/02 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L27/1207 ,  H01L21/02365 ,  H01L21/823431 ,  H01L21/8258 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/1033 ,  H01L29/1037 ,  H01L29/16 ,  H01L29/20 ,  H01L29/785

摘要： A method of forming fins of different materials includes providing a substrate with a layer of a first material having a top surface, masking a first portion of the substrate leaving a second portion of the substrate exposed, etching a first opening at the second portion, forming a body of a second material in the opening to a level of the top surface of the layer of the first material, removing the mask, and forming fins of the first material at the first portion and forming fins of the second material at the second portion. A finFET device having fins formed of at least two different materials is also disclosed.

摘要翻译： 形成不同材料的散热片的方法包括：提供具有顶表面的第一材料层的衬底，掩蔽衬底的第一部分，留下衬底的第二部分，蚀刻第二部分的第一开口，形成 在所述开口中的第二材料的主体到所述第一材料的所述层的顶表面的高度，去除所述掩模，以及在所述第一部分处形成所述第一材料的翅片，并在所述第二部分处形成所述第二材料的翅片 。 还公开了具有由至少两种不同材料形成的翅片的finFET器件。

公开(公告)号：US20150031192A1

公开(公告)日：2015-01-29

申请号：US14383520

申请日：2013-02-20

申请人： OSRAM Opto Semiconductors GmbH

发明人： Thomas Bauer

IPC分类号： H01L21/687 ,  B05C13/02 ,  H01L21/02 ,  C23C16/458

CPC分类号： H01L21/68742 ,  B05C13/02 ,  C23C16/458 ,  H01L21/02365 ,  H01L21/67109

摘要： A substrate carrier arrangement (10, 11) for a coating system (12) is provided, comprising a carrier (1) which comprises at least one support region (3) having a support surface (30), on which a substrate support (2) is arranged, and which support region comprises in the support surface (30) at least one first and one second gas inlet (4, 5), wherein the first gas inlet (4) is at a smaller distance from a center (M) of the support surface (30) than the second gas inlet (5) and wherein the first and second gas inlet (4, 5) comprise mutually independent gas feeds (40, 50) which are arranged to supply gases having mutually different thermal conductivities. A coating system comprising a substrate carrier arrangement and a method for performing a coating process are also provided.

摘要翻译： 提供了一种用于涂层系统（12）的衬底载体布置（10,11），其包括载体（1），所述载体（1）包括至少一个具有支撑表面（30）的支撑区域（3），衬底支撑件 ），并且所述支撑区域在所述支撑表面（30）中包括至少一个第一和第二气体入口（4,5），其中所述第一气体入口（4）距离中心（M）更小的距离， 所述第一和第二气体入口（4,5）包括彼此独立的气体进料（40,50），所述气体进料被配置成供应具有相互不同热导率的气体。 还提供了一种包括基板载体装置和用于执行涂布工艺的方法的涂覆系统。

公开(公告)号：US20140346461A1

公开(公告)日：2014-11-27

申请号：US14067230

申请日：2013-10-30

申请人： Samsung Display Co., Ltd.

发明人： Kwang-Hae KIM ,  Jae-Beom CHOI ,  Kwan-Wook JUNG

IPC分类号： H01L27/12 ,  H01L27/32

CPC分类号： H01L29/66765 ,  H01L21/02107 ,  H01L21/02365 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32133 ,  H01L21/3215 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/127 ,  H01L27/1288 ,  H01L27/3244 ,  H01L27/3248 ,  H01L27/3262 ,  H01L27/3265 ,  H01L29/66772 ,  H01L2227/323

摘要： A thin film transistor (TFT) substrate, an organic light-emitting display apparatus including the TFT substrate, and a method of manufacturing the TFT substrate that enable simple manufacturing processes and a decrease in the interference between a capacitor and other interconnections are disclosed. The TFT substrate may include a substrate, a TFT arranged on the substrate, the TFT including an active layer, a gate electrode, a source electrode, and a drain electrode, a pixel electrode electrically connected to one of the source electrode and the drain electrode, and a capacitor including a lower capacitor electrode and an upper capacitor electrode, the lower capacitor electrode formed from the same material as the active layer and arranged on the same layer as the active layer, and the upper capacitor electrode formed from the same material as the pixel electrode.

摘要翻译： 公开了一种薄膜晶体管（TFT）基板，包括TFT基板的有机发光显示装置和制造TFT基板的方法，其使制造工艺简单，电容器与其它互连之间的干涉减小。 TFT基板可以包括衬底，布置在衬底上的TFT，包括有源层的TFT，栅电极，源电极和漏电极，电连接到源电极和漏极之一的像素电极 以及包括下电容电极和上电容电极的电容器，所述下电容电极由与所述有源层相同的材料形成，并且与所述有源层配置在同一层上，所述上电容器电极由与所述有源层相同的材料形成， 像素电极。

公开(公告)号：US20140242759A1

公开(公告)日：2014-08-28

申请号：US14274846

申请日：2014-05-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang

IPC分类号： H01L29/66 ,  H01L21/02

CPC分类号： H01L21/0254 ,  H01L21/02365 ,  H01L21/02381 ,  H01L21/02455 ,  H01L21/02458 ,  H01L21/02658 ,  H01L29/66446 ,  H01L29/66522 ,  H01L33/007

摘要： Provided is a method of fabricating a semiconductor device. The method includes providing a silicon substrate having opposite first and second sides. At least one of the first and second sides includes a silicon (111) surface. The method includes forming a high coefficient-of-thermal-expansion (CTE) layer on the first side of the silicon substrate. The high CTE layer has a CTE greater than the CTE of silicon. The method includes forming a buffer layer over the second side of the silicon substrate. The buffer layer has a CTE greater than the CTE of silicon. The method includes forming a III-V family layer over the buffer layer. The III-V family layer has a CTE greater than the CTE of the buffer layer.

公开(公告)号：US08779512B2

公开(公告)日：2014-07-15

申请号：US13849971

申请日：2013-03-25

申请人： NEC Corporation ,  NLT Technologies, Ltd.

发明人： Shigeru Mori

IPC分类号： H01L21/76

CPC分类号： H01L23/28 ,  H01L21/02365 ,  H01L29/02 ,  H01L29/66757 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.

摘要翻译： 提供一种半导体器件，其中半导体层形成在绝缘基板上，其中插入在半导体层和绝缘基板之间的前端绝缘层，其能够防止绝缘基板中包含的杂质对半导体层的作用 并提高半导体器件的可靠性。 在TFT（薄膜晶体管）中，使硼被包含在距离绝缘基板的表面约100nm以下的区域中，使得硼浓度以平均速率降低约1/1000倍/ 1 从绝缘基板的表面朝向半导体层。

公开(公告)号：US20140087545A1

公开(公告)日：2014-03-27

申请号：US13955836

申请日：2013-07-31

申请人： TOYODA GOSEI CO., LTD.

发明人： Naoyuki NAKADA

IPC分类号： H01L21/02

CPC分类号： H01L21/02365 ,  C23C16/0218 ,  C23C16/0272 ,  C23C16/303 ,  H01L21/0242 ,  H01L21/0243 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02631 ,  H01L21/02658

摘要： The surface of a sapphire substrate having a c-plane main surface is patterned by ICP dry etching. The patterned sapphire substrate is thermally treated in a hydrogen or nitrogen atmosphere at a temperature of less than 700° C. or at a temperature of more than 800° C. to 1100° C. An AlN buffer layer is formed by magnetron sputtering on the surface on the patterned side of the sapphire substrate heated at a temperature of 200° C. to less than 700° C. On the buffer layer, a Group III nitride semiconductor layer having a c-plane main surface is formed so as to have a thickness of 1 μm to 10 μm by MOCVD.

摘要翻译： 具有c面主表面的蓝宝石衬底的表面通过ICP干蚀刻图案化。 图案化蓝宝石基板在氢或氮气氛中在小于700℃或大于800℃至1100℃的温度下进行热处理。通过磁控管溅射形成AlN缓冲层 在200℃至小于700℃的温度下加热的蓝宝石衬底的图案侧上的表面。在缓冲层上形成具有c面主表面的III族氮化物半导体层，以具有 厚度为1μm〜10μm，通过MOCVD。

公开(公告)号：US08536021B2

公开(公告)日：2013-09-17

申请号：US13684623

申请日：2012-11-26

申请人： IO Semiconductor, Inc.

发明人： Anton Arriagada ,  Michael A. Stuber ,  Stuart B. Molin

IPC分类号： H01L21/30

CPC分类号： H01L29/0692 ,  H01L21/02365 ,  H01L21/2007 ,  H01L21/268 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76243 ,  H01L21/76251 ,  H01L21/7806 ,  H01L21/84 ,  H01L25/00 ,  H01L27/1203 ,  H01L29/7803

摘要： A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.

公开(公告)号：US20130207127A1

公开(公告)日：2013-08-15

申请号：US13372246

申请日：2012-02-13

申请人： Fei Yu ,  Qi Deng

发明人： Fei Yu ,  Qi Deng

IPC分类号： H01L33/48

CPC分类号： H01L25/167 ,  G02B6/4214 ,  G02B6/4246 ,  G02B6/428 ,  H01L21/02365 ,  H01L2224/16

摘要： An integrated circuit package includes a substrate having a recess formed along at least a portion of a perimeter of the substrate, and an optical die having opto-electric circuitry, the optical die coupled to the substrate such that a portion of the optical die with the opto-electric circuitry overhangs the recess. The integrated circuit package also includes an optical unit disposed in the recess such that optical signals emitted by the opto-electric circuitry are reflected away from the substrate and incident optical signals are reflected onto the opto-electric circuitry.

摘要翻译： 集成电路封装包括具有沿着衬底的周边的至少一部分形成的凹部的衬底和具有光电电路的光学管芯，该光学管芯耦合到衬底，使得光学管芯的一部分具有 光电电路突出了凹槽。 集成电路封装还包括设置在凹部中的光学单元，使得由光电电路发射的光信号被反射离开衬底并且入射光信号被反射到光电电路上。