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公开(公告)号：US11822934B2
公开(公告)日：2023-11-21
申请号：US17341054
申请日：2021-06-07
Inventor： Roberto Colombo , Om Ranjan
CPC classification number: G06F9/44505 , G06F11/1004 , G06F13/36 , H04L9/0643 , H04L9/3247
Abstract: A processing system includes a plurality of configuration data clients; each associated with a respective address and including a respective register, a hardware block, a non-volatile memory, and a hardware configuration circuit. A respective configuration data client receives a respective first configuration data and stores it in the respective register. The hardware block is coupled to at least one of the configuration data clients and changes operation as a function of the respective first configuration data stored in the respective registers. The non-volatile memory includes second configuration data stored as data packets including the respective first configuration data and an attribute field identifying the respective address of one of the configuration data clients. The hardware configuration circuit sequentially reads the data packets from the non-volatile memory and transmits the respective first configuration data to the respective configuration data client.
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公开(公告)号：US20230350483A1
公开(公告)日：2023-11-02
申请号：US18338950
申请日：2023-06-21
Inventor： Nitin CHAWLA , Anuj GROVER , Giuseppe DESOLI , Kedar Janardan DHORI , Thomas BOESCH , Promod KUMAR
IPC: G05F3/24 , G11C11/413 , G06F1/3234 , G06F1/3287 , G06F15/78
CPC classification number: G06F1/3275 , G05F3/24 , G06F1/3287 , G06F15/7821 , G11C11/413
Abstract: Systems and devices are provided to enable granular control over a retention or active state of each of a plurality of memory circuits, such as a plurality of memory cell arrays, within a memory. Each respective memory array of the plurality of memory arrays is coupled to a respective ballast driver and a respective active memory signal switch for the respective memory array. One or more voltage regulators are coupled to a ballast driver gate node and to a bias node of at least one of the respective memory arrays. In operation, the respective active memory signal switch for a respective memory array causes the respective memory array to transition between an active state for the respective memory array and a retention state for the respective memory array.
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公开(公告)号：US20230327667A1
公开(公告)日：2023-10-12
申请号：US18334989
申请日：2023-06-14
Applicant: STMicroelectronics International N.V.
Inventor： Vaibhav GARG , Abhishek JAIN , Anand KUMAR
IPC: H03K17/687 , H03K17/693 , H03K19/017
CPC classification number: H03K17/6872 , H03K17/6874 , H03K17/693 , H03K19/01735
Abstract: A multiplexer includes an input, an output, and a main switch configured to pass a signal from the input to the output. The multiplexer includes two bootstrap circuits that collectively maintain a constant voltage between terminals of the main switch during alternating phases.
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公开(公告)号：US20230314791A1
公开(公告)日：2023-10-05
申请号：US17711780
申请日：2022-04-01
Applicant: STMicroelectronics International N.V.
Inventor： Nenad NESTOROVIC , Jack SCHMIDT
CPC classification number: G02B26/0841 , G02B27/0955 , G01S7/4815 , G01S7/4817 , G02B26/10
Abstract: Disclosed herein is an efficient optical scanning system takes the output of a multi-laser bar emitter with high divergence and delivers a combined beam of long vertical stripes of optical power that have a nearly top hat distribution along a vertical scanning axis and a narrow width along a horizontal scanning axis. This line footprint of the combined beam is scanned by a mirror onto a scene for use as ranging light in a distance measurement system.
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公开(公告)号：US20230296868A1
公开(公告)日：2023-09-21
申请号：US17699958
申请日：2022-03-21
Applicant: STMicroelectronics International N.V.
Inventor： Nenad NESTOROVIC
CPC classification number: G02B17/0657 , G02B26/101 , G02B26/0833 , G02B27/0172 , G02B6/4215 , G02B17/023 , G01S7/4817 , G02B2027/011
Abstract: An optical module includes a fast-axis mirror that scans a laser beam along a fast-axis, a magnification mirror set formed by three discrete mirrors shaped to magnify the laser beam as it is scanned along the fast-axis and reflect the laser beam after magnification toward a slow-axis mirror that scans the laser beam along the slow-axis, and an Offner mirror relay that receives the laser beam as it is scanned along the slow-axis and reflects the laser beam out an exit aperture. The laser beam as output from the exit aperture is received at an input diffractive grating of a diffractive waveguide, with a user's eye being positioned adjacent an output diffractive grating of the waveguide such that the user's eye views ambient light entering the waveguide from objects within the user's field of view as well as light from the laser beam as it exits the output diffractive grating.
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Patent Agency Ranking
公开(公告)号：US11764807B2
公开(公告)日：2023-09-19
申请号：US17858782
申请日：2022-07-06
Inventor： Vivek Mohan Sharma , Roberto Colombo
CPC classification number: H03M13/1105 , H03M13/611
Abstract: A processing system is described. The processing system comprises a microprocessor, a memory controller, a resource and a communication system. The microprocessor is configured to send read requests in order to request the transmission of first data, or write requests comprising second data. The memory controller is configured to read third data from a memory. The processing system comprises also a safety monitor circuit comprising an error detection circuit configured to receive data bits and respective Error Correction Code, ECC, bits, wherein the data bits correspond to the first, second or third data. The safety monitor circuit calculates further ECC bits and generates an error signal by comparing the calculated ECC bits with the received ECC bits. A fault collection and error management circuit receives the error signal from the safety monitor circuits. For example the safety monitor circuit comprises a test circuit configured to provide modified data bits and/or modified ECC bits to the error detection circuit as a function of connectivity test control signals, whereby the error detection circuit asserts the error signal as a function of the connectivity test control signals. The processing system comprises also a connectivity test control circuit comprising control registers programmable via the microprocessor, wherein the connectivity test control signals are generated as a function of the content of the control registers.
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公开(公告)号：US11756899B2
公开(公告)日：2023-09-12
申请号：US17322712
申请日：2021-05-17
Inventor： Paolo Crema , Jürgen Barthelmes , Din-Ghee Neoh
IPC: H01L23/00 , C25D3/38 , C25D5/10 , C25D5/48 , H01L21/48 , H01L23/31 , H01L23/495 , C25D5/00 , C25D7/00
CPC classification number: H01L23/562 , C25D3/38 , C25D5/10 , C25D5/48 , C25D5/605 , C25D5/611 , C25D7/00 , H01L21/4825 , H01L23/3114 , H01L23/4952 , H01L23/49513 , H01L23/49541 , H01L23/49582
Abstract: The present disclosure is directed to a lead frame design that includes a copper alloy base material coated with an electroplated copper layer, a precious metal, and an adhesion promotion compound. The layers compensate for scratches or surface irregularities in the base material while promoting adhesion from the lead frame to the conductive connectors, and to the encapsulant by coupling them to different layers of a multilayer coating on the lead frame. The first layer of the multilayer coating is a soft electroplated copper to smooth the surface of the base material. The second layer of the multilayer coating is a thin precious metal to facilitate a mechanical coupling between leads of the lead frame and conductive connectors. The third layer of the multilayer coating is the adhesion promotion compound for facilitating a mechanical coupling to an encapsulant around the lead frame.
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公开(公告)号：US20230281092A1
公开(公告)日：2023-09-07
申请号：US18317420
申请日：2023-05-15
Applicant: STMicroelectronics International N.V.
Inventor： Avneep Kumar Goyal
IPC: G06F11/263 , G06F1/06 , G06F11/22
CPC classification number: G06F11/263 , G06F1/06 , G06F11/2236
Abstract: An apparatus includes a main core processor configured to receive a first signal through a first main buffer, a second signal through a second main buffer, a third signal through a third main buffer, and a fourth signal through a fourth main buffer, a shadow core processor configured to receive the first signal through a first shadow buffer, the second signal through a second shadow buffer, the third signal through a third shadow buffer and the fourth signal through a fourth shadow buffer, and a first glitch suppression buffer coupled to a common node of an input of the first main buffer and an input of the first shadow buffer.
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公开(公告)号：US20230275586A1
公开(公告)日：2023-08-31
申请号：US18098421
申请日：2023-01-18
Applicant: STMicroelectronics International N.V.
Inventor： Sandeep KAUSHIK , Paras GARG
IPC: H03K19/0185 , H03K17/687 , H03K19/017
CPC classification number: H03K19/018514 , H03K19/018585 , H03K17/6871 , H03K19/01707
Abstract: A Low Voltage Differential Signaling (LVDS) transmitter includes driver circuit with a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor. The first transistor is coupled between a first node and first output. The second transistor is coupled between the first node and a second output. The third transistor is coupled between the first output and a second node. The fourth transistor is coupled between the second output and the second node. The first resistor is coupled between the first output and a common mode node. The second resistor is coupled between the second output and the common mode node. A pre-driver circuit generates gate control signals controlling the first, second, third, and fourth transistors in response to a data signal. A controlled timing delay is applied to the timing of logic state transistors for the control signals.
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公开(公告)号：US11726514B2
公开(公告)日：2023-08-15
申请号：US17242067
申请日：2021-04-27
Applicant: STMicroelectronics International N.V.
Inventor： Shashwat , Rajesh Narwal
Abstract: An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.
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